| dc.description.abstract | In this thesis, a module generator, which can automate the process of designing high-speed low-complexity multirate multistage digital FIR filter / decimator / interpolator, is presented. The generator exploits architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. The input of the generator requires only system-level specifications. In addition, the generator can provide three types of filter structure for different applications. Moreover, the output is a synthesizable Verilog code written in behavioral-level hardware description language (HDL) which allows the synthesis tool to select the appropriate architecture from user’s constraints. Therefore, this tool can eliminate manual calculations, coding, simulation, and verification time of the design cycle.
We have designed several filters with TSMC 0.25μm standard cell. A 64-QAM baseband design example shows that the area is reduced about 1.64 times and the power dissipation is saved about 1.95 times for low-complexity applications. Moreover, for high-speed application, the chip can operate at 714MHz. Besides, we design the IFIR filters which specification is the first version of the CDMA cellular, the area is reduced about 1.72 times and the power dissipation is saved about 13.10 times as compared with direct form design. An example of multistage decimator used in CDMA cellular shows that the area is reduced about 3.56 times and the power dissipation is saved about 1.96 times as compared with conventional decimator. Finally, an example of the narrowband multistage interpolator are designed, the area is reduced about 3.06 and the power dissipation is saved about 1.36 times as compared with conventional interpolator. | en_US |