| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 蔡文洲 | zh_TW |
| DC.creator | Wen-Chou Tsai | en_US |
| dc.date.accessioned | 2004-7-16T07:39:07Z | |
| dc.date.available | 2004-7-16T07:39:07Z | |
| dc.date.issued | 2004 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=91521036 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 摘要
在本論文中，利用ICP與smart-EPDTM製作出超淺接面源/汲極結構，並且搭配高溫濕氧化(wet oxidation)將受損的表面氧化後，由氫氟酸水溶液將氧化後的缺陷層移除，完成淺接面源/汲極結構的製作。
本論文的另一重點為異質矽鍺/矽pn二極體的製作。利用LPCVD成長複晶矽鍺材料並以黃光設備搭配電漿蝕刻回蝕刻技術將pn二極體圖形定義出來，完成製作嵌入式/提升式異質矽鍺/矽pn二極體。而在元件直流特性上，嵌入式異質矽鍺/矽pn二極體無論是在開啟電壓(Von)、理想因數(n)、逆向飽和電流(Isat)與崩潰電壓(Vbd)有較佳的特性表現，同時也展現此異質結構較不易受鍺含量多寡的限制以及有效的抑制短通道效應，具實現高速與低功率消耗的元件設計之潛能。
運用嵌入式異質矽鍺/矽結構於MOSFETs的源/汲極上將可壓縮短通道效應，實現未來奈米金氧半電晶體發展之趨勢。因此，嵌入式矽鍺源極/汲極結構的確是一個適合運用於尺寸小、速度快與消耗功率低的奈米電子元件。 | zh_TW |
| dc.description.abstract | Abstract
In this thesis, we fabricated shallow junction S/D structure by ICP and smart-EPDTM. We applied high temperature wet oxidation to oxidize the defective surface. The oxidized defective layer was then removed by hydrofluoric (HF) acid.
We also fabricated hetero-SiGe/Si P-N diode. We first grew poly-SiGe material by LPCVD. The recessed/raised P-N diode was then patterned by yellow light equipments and plasma-etching-back techniques. As for DC characteristics, the recessed P-N diode performs better in turn on voltage (Von), ideality factor (n), reverse saturation current (Isat), junction capacitance (Cj), and breakdown voltage (Vbd). We also show that the recessed heterostructure is less dependent on the Ge content and effectively suppresses short-channel-effect. Therefore, the recessed hetero-SiGe/Si P-N diode is one of the best candidates to realize high speed and low power consumption.
By incorporating recessed hetero-SiGe/Si structure into the S/D of MOSFETs, we can compress short-channel-effect, and thus continue the scaling trend of MOSFETs into the nano-scale region. Therefore, recessed SiGe/Si S/D structure can realize nano-scale electronic devices with high speed and low power consumption. | en_US |
| DC.subject | 超淺接面源/汲極結構 | zh_TW |
| DC.subject | 高溫濕氧化 | zh_TW |
| DC.subject | 異質矽鍺/矽pn二極體 | zh_TW |
| DC.subject | 嵌入式/提升式異質矽鍺/矽pn二極體 | zh_TW |
| DC.subject | 開啟電壓 | zh_TW |
| DC.subject | 理想因數 | zh_TW |
| DC.subject | 逆向飽和電流 | zh_TW |
| DC.subject | 崩潰電壓 | zh_TW |
| DC.subject | 金氧半電晶體 | zh_TW |
| DC.subject | shallow junction S/D structure | en_US |
| DC.subject | turn on voltage | en_US |
| DC.subject | ideality factor | en_US |
| DC.subject | reverse saturation current | en_US |
| DC.subject | junction capacitance | en_US |
| DC.subject | breakdown voltage | en_US |
| DC.subject | short-channel-effect | en_US |
| DC.subject | wet oxidation | en_US |
| DC.subject | hetero-SiGe/Si P-N diode | en_US |
| DC.subject | recessed/raised P-N diode | en_US |
| DC.title | 矽鍺異質源/汲極結構與pn二極體之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Study and Processing of Hetero-SiGe/Si S/D Structure and P-N Diode | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |