| dc.description.abstract | This thesis covers the design of low-power high-linearity CMOS mixers. In the first part of this dissertation, a cascode dual-gate CMOS model is presented. The proposed large-signal model consists of two intrinsic conventional BSIM3v3 nonlinear models and the passive network represents the physical-based parasitic components of the device. The extrinsic elements of substrate networks, and the distributed resistances and inductances of gate, source and drain terminals are calculated from the measured S-parameters. Good agreement form 50 MHz to 15 GHz has been obtained between simulation and measurement of small-signal S-parameters and power characteristics. In order to verify the model accuracy, a 2.4 GHz dual-gate LNA and mixer were designed and tested. Moreover, a new third-order transconductance (gm3) cancellation technique is proposed and applied to a 2.4 GHz conventional RF mixer for improving circuit linearity. The bulk-to-source voltage is applied to adjust the peak value position of gm3. The cancellation of gm3 is utilized by a negative peak gm3 transistor combining in parallel with a positive peak gm3 transistor. For a single device, the measured adjacent channel power ratio (ACPR) and third-order intermodulation (IMD3) distortion are both improved over 15 dB. The compensated gm3 device is placed in the input RF gm-stage, thus reducing the principle nonlinearity source of the mixer. From the experiment results, the ACPR and IMD3 of the mixer are improved about 10 dB and 15 dB, respectively. An ultra broadband low-voltage low-power down-conversion mixer using a 0.18-µm standard CMOS process is also presented. The proposed mixer uses a novel cascode topology with a bulk-injection technique to achieve low-voltage and low-power performance. The mixer features a maximum conversion gain of 6 dB at radio frequency (RF) of 2.4 GHz, a single-side band (SSB) noise figure of 15.2 dB, and an input IP3 of 0 dBm. Moreover, the chip area of the mixer core is only 0.15 × 0.23 mm2. The measured 3-dB RF frequency bandwidth is from 0.5 to 6 GHz with an intermediate frequency (IF) of 100 MHz. The optimum dc supply voltage (VDD) can be scaled down to 0.7 V with a 0.4 mA drain current. The supply voltage and dc power of this circuit can be compatible with an advanced 90-nm or 60-nm CMOS technology. In the last part of this dissertation, a high quality-factor active inductor has been demonstrated. By adding a feedback resistance and a regulated gain stage transistor into the conventional cascade-grounded approach, the quality-factor and performance of CMOS active inductor can be improved. This novel active inductor demonstrated a maximum quality-factor of 540 and a 3.2 nH inductance at 4.3 GHz, where the self-resonant frequency was 5.4 GHz. An active CMOS band-pass filter was also fabricated including this tunable high quality factor active inductor, giving an insertion loss of 0.2 dB and a return loss more than 32 dB with a tuning range from 3.45 GHz to 3.6 GHz. | en_US |