| dc.description.abstract | The framework of extreme-voltage stress test system has been developed to reduce the lost yield caused by gate-oxide defects. However, the framework was developed for the gate-oxide defects that assume with 1/E model, where such a defect model is applicable for the oxide thickness above 5nm. For practical designs with the process of .18 um or below, the oxide thickness is less than 5nm, and thus the defect model with 1/E model may not be applicable accurately. In this study, the defect model with E model will be considered, where the oxide thickness is ranged between 2.7nm to 18.1nm. Therefore, the lifetime and failure rate of intrinsic oxide breakdown can be predicted for a given stress condition.
This thesis demonstrates the methodology that generates the stress vector and deals with stressability enhancement of portions of the circuit having poor stressability. A stressability enhancement strategy using additional hardware is also presented.
In order to demonstrate the developed stress test generation process, we demonstrates the applications of such process to both CMOS SRAM and PLL. It will show that both circuits may pass the conventional Iddq-tests in the presence of gate-oxide defects that occur at some transistors, causing a low reliability. Therefore, semiconductor manufacturers need to take alternative stress tests, expensive burn-in tests, to enhance gate-oxide reliability. However, with the developed stress test vectors, both circuits are fully stressed. As a result, the circuit can achieve a full gate-oxide reliability under the extreme-voltage stress tests without the need of the expensive burn-in tests. | en_US |