| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 卓峰信 | zh_TW |
| DC.creator | Feng-Hsin Cho | en_US |
| dc.date.accessioned | 2005-7-21T07:39:07Z | |
| dc.date.available | 2005-7-21T07:39:07Z | |
| dc.date.issued | 2005 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=92521024 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在網路以及電腦資料處理速度演進的帶動下，興起高速串列資料傳輸研究的潮流。鎖相迴路與時脈資料回復電路在運用常見有兩大類。其一是在乙太網路以及光纖網路上的應用(例如：10GBase-LX4、OC192等等)；另一方面則著重在有線或晶片內部的串列資料傳輸的應用(例如USB2.0、IEEE1394b、SERIAL-ATA、PCI-EXPRESS)，現有產品中PCI-Express V1目前之速率已高達2.5Gb/s，因此本論文以CMOS製程實現接收端之相關電路設計技術，目為實現一個在接收端2.5Gb/s資料回復電路。 本論文提出一個使用3倍超取樣技術的資料回復電路，其功能是將串列的訊號轉換回平行的資料。藉由延遲鎖定迴路產生的相位，可對串列訊號做3倍取樣，此資料回復器不僅可決定出最佳的取樣點、亦可找到資料的起始位置。在決定最佳取樣點方面，應用數位電路控制來決策出最佳參考相位，進而得到資料的最佳取樣邊界(Margin)。 本論文使用TSMC 0.18um 1P6M CMOS Process，設計出一個2.5Gbps傳輸率之資料回復電路。在2.5Gbps的資料率下可將串列資料成功的還原成四個625MB/s的並列輸出。此時核心電路的消耗功率為28.7mW | zh_TW |
| dc.description.abstract | Recently research on high speed link is more popular because of the progress of computer and network. The applications of phase locked loop and timing recovery are categorized to two types. One type is the application of Ethernet (such as 10GBase-LX4) and optical fiber (such as OC192 and OC768). Another is the application of Firewire (such as USB and IEEE1394) 、Chip to Chip and storage to storage (such as PCI-Express and Serial ATA).The available products of PCI-Express
X1 achieves the 2.5Gbps data transfer rate. Therefore, this thesis studies on the implementation and design of a 2.5GB/s data recovery circuit for high speed link in PCI-Express X1.
A 2.5GB/s data recovery circuit with 3 times oversampling technique is adopted.
Its main function is that to receive the serial input signal to parallel output. It samples data 3 times by the sampling clock generated from delay locked loop, so as to decide the best sampling point and data frames. It uses digital control circuit to realize the 3 times oversampling technique so that the input signal is sampled with the maximum timing margin.
A 2.5GBps data recovery system with 3 times oversampling technique has been designed and implemented by 0.18μm TSMC CMOS process. 2.5GBps data stream would be successfully received and synchronized to four parallel channels with 28.7mW power consumptions. | en_US |
| DC.subject | 時脈資料回復 | zh_TW |
| DC.subject | 資料回復 | zh_TW |
| DC.subject | data recovery | en_US |
| DC.subject | clock data recovery | en_US |
| DC.title | 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | 2.5GB/s CMOS Oversampling Data Recovery Circuit for Serial Link Application | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |