| dc.description.abstract | Abstract
In this work, RF front-end circuit for WCDMA receiver is implemented by using tsmc SiGe 0.35?m BiCMOS process. This thesis is divided into two parts which are the analysis system-level specifications of WCDMA receiver and front-end circuits design. The first part is described in chapter 2, The detail derive of the receiver requirements according to the 3GPP specifications and standard testing are introduced. The required specifications are as following: NF<8.7dB, Adjacent-Channel Selectivity>34dB, IIP2>-15.6dBm, IIP3>-16.8dBm and Phase Noise<-129dBc @ 8MHz offset.
The second part of RF front-end circuit for WCDMA receiver is the main research in this thesis, such as low noise amplifier, micromixer, voltage-controlled oscillator and frequency divider designs. Following are the measured results of these designs.
Chapter 3 is micromixer design and the measurements of conversion gain is 8dB, input power at the 1-dB gain compression point is -12dBm, input third-order intercept point is 2dBm, all port-to-port isolations are greater than 23dB and IF bandwidth is 150MHz.
Chapter 4 is the design of differential variable gain LNA and the measurements of gain is 16.5dB, noise figure is 2.1dB, input power at the 1-dB gain impression point is -15dBm, input third-order intercept point is -2dBm and gain control range is 11dB.
Chapter 5 is the design of fully differential variable gain receiver and the measurements of conversion gain is 16dB, noise figure is 3.2dB, input power at the 1-dB gain impression point is -30dBm, input second-order intercept point is 25dBm, input third-order intercept point is -17dBm, all port-to-port isolation is greater than 32dB and gain control range is 11dB.
Chapter 6 is the design of differential Colpitts VCO and frequency divider, the measurements of 2.15GHz VCO are as following: phase noise: -97dBc/Hz @100KHz offset, output power: -9dBm and tuning range: 225MHz. The measurements of 4.3GHz VCO and frequency divider are following: phase noise: -94.6dBc/Hz @100KHz offset, output power: -6dBm, tuning range: 379MHz and divider output power is -8.58dBm. | en_US |