| dc.description.abstract | Due to the ability of integration many modules with different functions, the system-on-chip is becoming a very interesting solution system method. However, on-chip interconnects that transmit signals between inter-modules limit the performance of chip due to long wire delay, large area, large power consumption and high interconnect complexity. It is especially serious in global on-chip interconnect.
Therefore, in this thesis, we firstly analyze characteristics and trends of the on-chip interconnect with scaling technology nodes. In terms of these analyses, we can establish more accurate interconnect models and it is useful in designing circuits for interconnetcs. Besides, we use serial link technique in on-chip application. With the interconnects models, we design a serial transceiver and a parallel transceiver for comparison. The advantages of serial transceiver are to reduce the interconnect area, reduce interconnect complexity without sacrificing the operational speed of system.
We adopt tsmc 0.13 um 1P8M CMOS process to implement our design, and the operational speed are 5 Gbps and 4 Gbps respectively. The power consumption per channel are 0.8 mW and 2.7 mW respectively, and the interconnect area of serial transceiver is half of parallel one at same operational speed. | en_US |