| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 張書銘 | zh_TW |
| DC.creator | Shu-Ming Chang | en_US |
| dc.date.accessioned | 2005-7-16T07:39:07Z | |
| dc.date.available | 2005-7-16T07:39:07Z | |
| dc.date.issued | 2005 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=92521035 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 因為容易設計及穩定的特性，延遲鎖定迴路(Delay-Locked Loop)已經比鎖相迴路(Phase-Locked Loop)更廣泛地應用在時脈誤差調整上。不僅如此，在現今有越來越多的應用開始使用延遲鎖定迴路，例如本地震盪電路與時脈產生器，而這一些應用在以前只能使用鎖相迴路。因此，在不久的未來，延遲鎖定迴路將會更加重要
在本論文中主要針對延遲鎖定迴路及其多重相位倍頻器與差動倍頻器作出說明以及討論，並且使用TSMC 0.18μm 1P6M CMOS Process，供應電壓為1.8V；設計出一個1.28GHz延遲迴路倍頻器。其延遲鎖定迴路的輸入範圍為220MHz~320MHz，多重相位倍頻器輸出時脈倍數可利用數位信號控制來達成，頻率倍數為1x、2x及4x；另外差動倍頻器則會直接合成出2x及4x的訊號。輸出頻率為220MHz ~ 320MHz (1倍頻)、440MHz ~ 640MHz (2倍頻)、880MHz ~ 1.28GHz (4倍頻)，電路操作於1.0GHz輸出時脈之峰對峰擾動值分別為32.7ps與54.49ps，其功率消耗為67.16mW。 | zh_TW |
| dc.description.abstract | Delay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. In nowadays, more and more applications, such as local oscillator and clock generator where only used with PLL in the past and are employed DLLs. So, the DLLs will be more significant in the near future.
The main object of this thesis is the description and discussion in Delay-Locked Loop, multiphase edge combiner and fully differential edge combiner; uses TSMC 0.18μm 1P6M CMOS process to design a 1.28GHz DLL-based frequency multiplier and the supply voltage is 1.8V. The operate frequency range of DLL is 220MHz to 329MHz; the multiple factor of the multiphase edge combiner can easily use with digital control code and the multiple factor is 1x, 2x and 4x. Besides, the fully differential edge combiner can directly synthesize the 2x and 4x output signals. The synthesized frequencies of the DLL-based frequency multiplier are 220MHz to 320MHz (multiply-by-1), 440MHz to 640MHz (multiply-by-2) and 880MHz to 1.28GHz (multiply-by-4). The power dissipation and peak-to-peak jitters are 67.16mW and 32.7ps, 54.49ps at 1.0GHz output clock frequency. | en_US |
| DC.subject | 延遲鎖定迴路 | zh_TW |
| DC.subject | 倍頻器 | zh_TW |
| DC.subject | Delay-Locked Loop | en_US |
| DC.subject | frequency multiplier | en_US |
| DC.title | 多重相位之延遲鎖定迴路倍頻器設計與分析 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and Analysis of Multiphase DLL-based Frequency Multipliers | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |