| dc.description.abstract | Nowadays, verification is still a primary bottleneck in the design flow. While using the simulation acceleration techniques to speed up the simulation-based verification, the communication overhead between the host machine and accelerator often appears as an extra overhead that limits the obtained improvement. In addition, after the designs are put into the hardware-based accelerators, the poor visibility of internal signal becomes another issue while tracing the possible bugs. Therefore, the focuses of this dissertation are put on those two primary issues.
Due to the communication overhead between hardware and software, traditional simulation acceleration has to compromise between testbench compatibility and performance. In this dissertation, a new approach, named as Hybrid Embedded Testbench Acceleration (HETA), is proposed to reduce this communication overhead. This method can avoid the communication issue and greatly improve the simulation speed. Experimental results on an industry case show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator with only 0.57% hardware overhead. This demonstrated that HETA is an efficient solution to further reduce the simulation time for functional verification with less overhead.
Hardware prototype is very important in last stage of functional verification, due to its high simulation speed. However, it is very hard to debug using this approach due to poor visibility in the FPGA. Therefore, in this dissertation, propose another approach to “record” the internal behaviors of a FPGA and “replay” the interesting period of time in a software simulator. In this way, we can still have high simulation speed because most simulation efforts are still finished in the FPGA. Besides, full visibility and better debugging environment can be provided in the software simulation. The experimental results have shown the efficiency of using our approach.
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