| DC 欄位 |
值 |
語言 |
| DC.contributor | 工業管理研究所在職專班 | zh_TW |
| DC.creator | 陳君豪 | zh_TW |
| DC.creator | Chun-hao Chen | en_US |
| dc.date.accessioned | 2007-7-18T07:39:07Z | |
| dc.date.available | 2007-7-18T07:39:07Z | |
| dc.date.issued | 2007 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=93436006 | |
| dc.contributor.department | 工業管理研究所在職專班 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 晶圓製造完成後，會針對每個 IC 做完整晶圓測試 (Wafer testing)，確定是否可達成客戶的規格，並可供評估此批晶圓品質好壞的重要指標，以提升晶圓廠製程品質的穩定性，同時為提升測試良率，往往會重測 (Re-testing) 特定不良之 IC。 一般而言，不良 IC 的分類方法，是透過 Bin 數字分類 IC 上各種不同電性的指標，在分析過程中，首先測試工程師必須分析良率是否符合制定的目標值，如果良率低於目標值，可考慮針對特定不良 IC 執行重測，或甚至重測整片晶圓。由於不良率的原因可能來自於晶圓廠製程異常、測試設備不穩定，或是因測試作業不當而造成；然而大部分工程師所關心的，除了須分析造成良率異常的原因外，更想了解在重測後良率是否可提高，期望在重測後的良率比未重測前能明顯提高，因此為了提升晶圓的良率，往往只注意良率的變化，而未考量實際所帶來的重測效益。本研究收集案例公司於 95 年度晶圓測試良率資料、測試成本與產品利潤之相關資料供研究分析，論文首先探討案例中影響良率的關鍵因子，並透過類神經網路來預測各測試階段之良率，並尋找最適重測門檻值，符合最佳的測試流程，也希望為案例公司帶來最佳效益，為此論文之主要貢獻。 | zh_TW |
| dc.description.abstract | In order to verify whether wafer can be able to achieve expected specification, generally every die will be probed completely after being fabricated in wafer fab. By such operation, we can use the essential index to improve wafer foundry’s quality and also the yield of wafers. In the mean time, IC design house hopes to get better yield during wafer probing process, normally they will try to ‘re-test’low-yield-wafer, no matter re-test entire gross dies or particular defective dies.
In general, defective dies are classified by using different bin numbers; the bin numbers represent particular testing result or its performance. During failure analysis after finishing wafer testing, testing engineer can decide to re-test abnormal wafer directly if it’s out of yield limit set previously. As normally engineers just ‘hope’ to get higher yield recovered from second testing, they seldom know how to predict yield variation and regard the related profit before making decision of re-testing
Hence, this thesis attempts to propose a workable solution for wafer testing process by using Artificial Neural Back Propagation Network (BPN). Through a real example from CMOS Image Sensor probing process, it was presented to demonstrate the methodology. We finally hope to get the proper threshold for re-testing and also bring different opinion to the CMOS Image Sensor Company. | en_US |
| DC.subject | 類神經網路 | zh_TW |
| DC.subject | 重測門檻值 | zh_TW |
| DC.subject | 良率預測 | zh_TW |
| DC.subject | 晶圓測試 | zh_TW |
| DC.subject | Back-Propagation Network | en_US |
| DC.subject | Thresholds for re-testing | en_US |
| DC.subject | Wafer testing | en_US |
| DC.title | 以類神經網路探討晶圓測試良率預測與重測指標值之建立 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Using Artificial Neural Network to Predict Wafer Testing Yield and Establish Thresholds of Wafer Re-Testing | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |