| dc.description.abstract | Abstract
With advances in semiconductor fabrication technology, the minimum feature size continues to decrease and the circuit density increases gradually. At the same time, increasing clock speeds demands these circuits to switch at faster rates. Thus, noise generation becomes more and more serious in today’s high-speed circuits. Moreover, decreasing power supply voltages dictate lower transistor threshold voltage. Therefore, noise margins of circuits become smaller. It causes a significantly signal-to-noise ratio reduction for both digital and mixed-signal/analog circuits. Therefore, the circuit performance will be limited by noise.
In this thesis, we provide a noise-aware standard cell library. There are two major parts in the subject, noise characterization and noise suppression cell design. On noise characterization, we introduce the procedure to characterize the noise behavior and use CLKINVX1 and NAND2X1 as a characterization example. We also discuss the way to characterize simultaneous switching noise and propose some preliminary ideas.
On noise suppression cell design, we implement the passive power supply noise (PSN) suppression cell, decoupling capacitance, and an active PSN suppression module. They can be used to suppress PSN occurring in design’s circuit. The simulation results appeal that the active PSN suppression circuit can have 33% reduction for negative PSN peak and 44% reduction for positive PSN peak. Finally, we combine the active PSN suppression circuit with an on-chip bounce measurement circuit. This combined circuit can let us observe the improvement due to the active PSN suppression circuit directly. | en_US |