| dc.description.abstract | Astract
Yield and reliability are two important factors of the semiconductor products, it produces some defects in the course of making to cause some external situations in the course of making, but comparatively a common one is that the floodgate on MOS component oxidizes one story of questions had in CMOS IC, generally we call that Defect (defect ), this reason is very difficult to be found when IC was just made out, can make floodgate oxidize one layer of damage make the execution efficiency of the circuit lower greatly by the defect until after a while, want how discover and prevent similar situation from is it have methods appear to take place it ahead of time, more efficient way Burn-in at present (roast), this method is to send IC to while testing the case and utilize the side of high-temperature high pressure to show and let defective MOS circuit be damaged ahead of time, can prevent these products from flowing into the customer’’s hands once coming so, but this method has not only raised the cost of the products also increases a lot of test time.
Other ways use traditional Iddq Test and 0-1 Test but but the speech may actually not be suitable for imitating the circuit, it is that a way with high voltage pressurize to defective MOS so we adopt another way to examine, and then by to is it can calculate voltage that pressurize and why it will be pressurization time to derive us, how long is the acceptable time of MOS without defect of very accurate judging so once coming, MOS not reaching this time will be damaged, in this way we needn’’t spend too much time and money raising the reliability , so we select PLL (Phase Clock Loop ) to adopt the circuit that pressurize and test in imitating the circuit as this page thesis, and it is linear phase locking return circuits respectively that PLL can be divided into three kinds (Linear PLL), several type phase locking return circuit (Digital PLL ) and location type phase locking return circuit (ADPLL ) totally, linear phase locking return circuit among them make up by complete simulation circuit, totally the location type phase locking return circuit regards digit as the circuit become of structure for the whole circuit, and we several type phase locking return circuit, this at phase place frequency detect examining device change it several circuit structure their from original simulation circuit structure to in kinds of the characteristics of PLL on part imitate by circuit, so PLL that we selected this kind of modelling for use can prove that it can be to imitating the circuit or the digit circuit suitably to pressurize to test the way . | en_US |