| dc.description.abstract | In modern VLSI deigns, manufacturing issues have complicated the designs of chips as well as packages. Moreover, due to the requirement of the market, modern circuits have higher functionality, lower supply voltage and more I/Os. These conditions increase complexity of chip designs. In this dissertation, we present some I/O plan and floorplan methods to solve these problems. They cannot only be applied to mitigate the power supply noise in the core, but also can consider the package designs, and stacking IC designs.
For the simultaneous switching noise, our method adopts a two-stage technique of the floorplan followed by the decoupling capacitance (decap) insertion. In the floorplan, the area and noise are evaluated to find a noise-driven floorplanning result. Then, we use a noise-driven decap planning approach to inserting minimal decaps into a floorplan. For IR-drop and the packages issues, we adopt a finger/pad assignment method to solve these problems. Our finger/pad assignment is a two-step method: we first solve the package design problem, then try to minimize IR-drop by switching finger/pad locations. In addition, since stacking IC is promising to the development of a high-performance IC, in this dissertation, we propose a partition approach to minimizing the 3D-vias and balancing the I/O number for each tier in stacking IC. Finally, we perform a floorplanning to show the importance of the aspect-ratio factor in stacking IC.
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