| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳柏仁 | zh_TW |
| DC.creator | Po-Jen Chen | en_US |
| dc.date.accessioned | 2007-7-19T07:39:07Z | |
| dc.date.available | 2007-7-19T07:39:07Z | |
| dc.date.issued | 2007 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=945201007 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 此論文裡，我們提出了一套利用Verilog-A 的硬體描述語言來建立交換電容
式積分器(Switched-Capacitor Integrator)電路的理想行為模組。此目的為提升模擬
層級，縮短類比電路的模擬時間，使數位電路與類比電路可提早做整合，進而加
快了整個設計的流程。
在理想行為模組中，我們針對此積分器在時域上的行為進一步加以描述，使
得我們所建立的行為模組能更接近真實電路的行為。而在非理想效應中，除了積
分器增益(DC Gain)、積分器直流輸出電位的偏移(DC Level Offset)、積分器外部
轉換速率(Extermal Slew Rate)及開關熱雜訊(Switch Thermal Noise)外，我們又額
外考慮到其它幾項重要的非理想效應：積分器穏態響應(Settling Response)、運算
放大器之熱雜訊(Operational Amplifier Noise)及電源雜訊(Supply Voltage
Variation)。接下來我們建立一套標準的萃取模式(Extraction Mode)，利用由下而
上(bottom-up)的方法將實際電路的非理想因素萃取出來，再將這些非理想參數值
帶回理想的行為模組中，使得我們所建立出來的行為模組能真實反映出實際電路
的行為。
為了驗証我們的想法，以一個二階三角積分調變器為例，此調變器中包含上
述所考慮的交換電容式積分器，來証明我們的方法不僅可以大大的縮短模擬所需
的時間，在時域上，我們所建立出來的行為模型亦能接近實際電路的行為。而且
時域行為的精確，進而達成在頻域的部分也能符合實際電路的行為。 | zh_TW |
| dc.description.abstract | In order to reduce the simulation time of analog circuits, the simulation model needed to be raised to higher abstract level. Therefore, the ideal behavioral model of a switched-capacitor integrator has been developed by using Verilog-A Hardware Description Language in this thesis.
In our ideal model, the behavior of integrator in time-domain has been described more carefully to make our model more close to the real circuits. In the case of non-ideal effect in the integrator, not only the DC Gain, DC Level Offset, External Slew Rate and Switch Thermal Noise have been considered. We also consider several important non-ideal effects like Settling Time of integrator, Operational Amplifier Noise and Supply Voltage Variation. We build a standard extraction by using bottom-up method to extract those non-ideal parameters. After annotating those non-ideal parameters in to our ideal model, then the behavior of our developed model can be more close to real circuits.
In this thesis, we use a second-order sigma-delta modulator, which includes two switched-capacitor integrators, to verify our developed model. According to the experimental results, the behavior of our model can perform more close to the real circuits in time-domain. And due to the accurate time-domain behavior of our developed model, the behavior in frequency-domain can also fit the exact behavior of real circuits. The most important thing is that using our developed model can greatly reduce the simulation time instead of the traditional simulation methods. | en_US |
| DC.subject | 交換電容式積分器 | zh_TW |
| DC.subject | 三角調變積分器 | zh_TW |
| DC.subject | 行為模型 | zh_TW |
| DC.subject | sigma-delta modulator | en_US |
| DC.subject | Switched-Capacitor Circuit | en_US |
| DC.subject | Behavioral Model | en_US |
| DC.title | 以行為模型建立交換電容式積分器之非理想現象及準確時間響應的研究 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | On Behavioral Modeling of Switched-Capacitor Circuits with Non-Ideal Effects and Accurate Timing Response | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |