| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳保霖 | zh_TW |
| DC.creator | Bao-Lin Chen | en_US |
| dc.date.accessioned | 2007-7-23T07:39:07Z | |
| dc.date.available | 2007-7-23T07:39:07Z | |
| dc.date.issued | 2007 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=945201012 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本篇論文為實現多級與單級256-對-1類比多工器，僅採用NMOS傳輸閘作為開關閘，對此類比多工器提出突波分析並且比較突波造成開關位準不精確的原因，發現存在於多級架構多工器的關鍵路徑上，預先充電現象將會使得電路產生很嚴重的突波，所以得到單級256-對-1類比多工器是最佳的設計，同時我們再最佳化解碼器電路設計，使得突波從13.3 VLSB(多級)最後改善到0.5 VLSB(單級)。 | zh_TW |
| dc.description.abstract | This paper aims to implement an analog multiplexer by using only NMOS pass transistor as switching gate.Two types of structures including multi-stages and single-stage are compared to evaluate their circuit performance. For these analog multiplexers, glitch analysis is proposed and applied to explore the factor of inaccuracy of voltage level due to switching. It is shown that the mechanism of pre-charge will cause a serious glitch effect on the critical path of a multi-stages analog multiplexer. Finally the single-stage structure is adopted. By optimizing the design of the corresponding decoders, the glitch can be significantly reduced from 13.3 VLSB for multi-stages to 0.5 VLSB for single-stage. | en_US |
| DC.subject | 類比多工器 | zh_TW |
| DC.subject | Analog Multiplexer | en_US |
| DC.title | 電阻串數位類比轉換器之類比多工器設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of Analog Multiplexer in a Resistor-String DAC | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |