| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 徐紹華 | zh_TW |
| DC.creator | Shao-hua Hsu | en_US |
| dc.date.accessioned | 2007-10-16T07:39:07Z | |
| dc.date.available | 2007-10-16T07:39:07Z | |
| dc.date.issued | 2007 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=945201036 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著CMOS製程技術進入奈米時代，電子元件的發展越來越趨向小尺寸、高操作速度、與低消耗功率，因此許多奈米元件越來越受到重視，其中單電子電晶體具有以上優點之外，更被認為可以應用於記憶體、邏輯電路以及量子訊息等方面，所以單電子電晶體已開始倍受矚目。而在單電子電晶體中最重要的核心技術除了形成奈米等級的量子點之外，還有自我對準之閘電極的製作，以利於閘極有效地調變量子點內部能階，並且減少閘極引起穿隧接面降低的寄生效應。另外，一般製作矽基材量子點與單電子電晶體通常使用Silicon on Insulator或者Silicon Germanium on Insulator的結構與超高解析度之電子束微影技術，但通常伴隨著高成本與製程掌控不易等缺點。本實驗室已成功開發出利用〝矽鍺選擇性氧化法〞氧化複晶矽鍺形成鍺量子點，這是一種具有經濟效益且與CMOS製程相容的方法。
本論文之研究重點為成功地在非晶矽與氮化矽表面沈積複晶矽鍺薄膜，克服複晶矽鍺沈積於二氧化矽表面時的潛伏期，利用〝矽鍺選擇性氧化法〞氧化複晶矽鍺形成鍺量子點並且利用下閘電極製作鍺量子點單電洞電晶體。在室溫下觀察到明顯的庫倫震盪電流，以及有效地抑制了閘極引起穿隧接面降低的寄生效應，並且經由光的激發可以觀察到更明顯的庫倫震盪。除此之外，觀察穿隧電流在不同偏壓與溫度下的變化，探討元件之不對稱現象與背景電流的發生機制。 | zh_TW |
| dc.description.abstract | As CMOS technology is scaling into nanometer regime, the development of devices is towards small dimension, high speed, and low power consumption. Since single-electron (SE) device not only provide the aforementioned advantages but also could be applied to memory-devices, logic-devices and quantum information, the SE device has attracted lots of attention. In addition to forming a nano-scaled quantum dot (QD), it is also imperative for SE devices to form self-aligned gate and source/drain electrodes in order to manipulate the QD effectively and to suppress the gate-induced tunneling barrier lowering effect. However, the formation of SE devices from Silicon-on-Insulator(SOI) or SiGe-on-Insulator(SGOI) structures is usually with high cost and restricted design freedom. This motivates us to develop a simple method, “Selectivity oxidation of polycrystalline-SiGe” to form Ge QDs. It is a cost effective and CMOS compatible approach.
The main theme of this thesis is to suppress the large incubation time for poly-SiGe deposition onto silicon dioxide (SiO2) and to form uniform poly-SiGe thin film on amorphous-Si and silicon-nitride (Si3N4) surface. In addition, we make use of the selective oxidation of the poly-SiGe thin film to form uniformly distributed Ge QDs. Then we fabricate Ge-QD single-hole transistor (SHT) based on a bottom-gate technology. We have experimentally studied the electrical characteristics and photo-effect of the Ge-QD SHT. Clear Coulomb-blockade oscillation was observed at room temperature and the gate-induced tunneling barrier lowering effect is suppressed. Furthermore, enhanced Coulomb oscillation and peak-to-valley current ratio were realized under photo-excitation. Finally, we discussed the asymmetrical features and trap assisted carrier tunneling effect of this device. | en_US |
| DC.subject | 複晶矽鍺 | zh_TW |
| DC.subject | 鍺量子點 | zh_TW |
| DC.subject | 單電子 | zh_TW |
| DC.subject | 下閘電極 | zh_TW |
| DC.subject | 庫倫阻斷 | zh_TW |
| DC.subject | single electron | en_US |
| DC.subject | bottom-gate | en_US |
| DC.subject | Coulomb-blockade | en_US |
| DC.subject | polycrystalline-SiGe | en_US |
| DC.subject | Ge quantum dot | en_US |
| DC.title | 具有自我對準下閘電極鍺量子點單電洞電晶體之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Germanium quantum-dot single-hole transistors with self-aligned electrodes based on a bottom-gate technology | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |