dc.description.abstract | When the frequency of system clock is increasing in System-On-Chip (SoC), the efficiency of clock synchronization would affect the normal motion of the entire circuit. Therefore both Phase-locked Loop (PLL) and Delay-Locked Loop (DLL) are widely used in SoCs for many synchronization-dependent systems in order to suppress the clock skew. However, some issues shall be considered while using these two circuits. First of all, since it is closed-loop system, there would be problem of bandwidth, it rely on capacitance to increase the stability of the circuit. Secondly, these circuits would need hundreds clock cycles before locked, which consumed larger power during long locking process.
Consequently, synchronous mirror delay (SMD) is developed to reduce lock cycle and power consumption, and to replace PLL and DLL. However, there are three major defects in conventional SMD. Start with; the duty cycle for input signal is restricted. Next, the static phase error is large after locking. Finally, circuits would be affected by the change in output load, which makes the conventional synchronous mirror delay can be only used in memory module.
In order to enable synchronous mirror delay to be used in a wider range, a high precision fast locking arbitrary duty cycle clock synchronization circuit is introduced, which not only fix the defects of conventional SMD, but also gain the phase error between the input signal and output signal is less than 16.6 ps. And the tuning range of input signal’s duty cycle is 20% ~80%. The test chip is fabricated in a 0.13-μm, and the operating frequency is between 222~800MHz. It consumes 5.14mW and static phase error is 8.07ps when the frequency is 800MHz. The core area (without I/O PAD) is 0.015 mm2 , There will be a simulation result at the last half of this thesis, which confirms the proposed circuit has improved certainly these drawbacks of SMD.
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