博碩士論文 945301023 完整後設資料紀錄

DC 欄位	值	語言
DC.contributor	電機工程學系在職專班	zh_TW
DC.creator	洪國源	zh_TW
DC.creator	Kuo-yuan Hung	en_US
dc.date.accessioned	2008-6-27T07:39:07Z
dc.date.available	2008-6-27T07:39:07Z
dc.date.issued	2008
dc.identifier.uri	http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=945301023
dc.contributor.department	電機工程學系在職專班	zh_TW
DC.description	國立中央大學	zh_TW
DC.description	National Central University	en_US
dc.description.abstract	在三維的元件模擬中,傳統的分解法產生大量的非零項,它會消耗大量的記憶體空間。然而個人電腦的記憶體空間有其限制而且三維元件的立方體數也將會被限制。因此,在此篇論文中,我們提出了整合型帶狀不完全LU分解法與帶狀LU分解法的模擬器,它可改善記憶體空間不足的問題。我們透過三維的p-n diode來驗證這兩種分解法,並且提出兩種解法器的特性與差異。依據這兩種分解法的特性,我們可選擇合適的解法器來應用在不同的三維元件結構,使得我們的個人電腦能在三維元件特性模擬中發揮最大效能,達成節省記憶體空間的目的。我們也模擬了不同結構的MOSFET,進一步地分析與探討三維MOSFET的特性。	zh_TW
dc.description.abstract	In 3-D device simulation, there will have a lot of nonzero items in matrix solver and cost many memory space. However, the memory space has its limitation and the number of cubic grids will also be confined. In this thesis, we propose the integration matrix solver using Banded incomplete LU method and Banded LU method. The integration solver improves the problem that the memory space is insufficient. We use 3-D p-n device to verify our simulator and find out the feature between the two solvers. Based on the solver property, we select the suitable solver for corresponding 3-D structure. After that, our simulator can save the memory space and make our personal computer working effectively. Finally, we run the simulation of MOSFET in 3-D different structures to analyse the device characteristics.	en_US
DC.subject	邊界不完全LU分解法	zh_TW
DC.subject	三維元件模擬	zh_TW
DC.subject	3-D device simulation	en_US
DC.subject	BILU Solver	en_US
DC.title	Band解法器與BILU解法器應用於三維元件模擬之整合	zh_TW
dc.language.iso	zh-TW	zh-TW
DC.title	Integration of Band Solver and BILU Solver for 3-D Device Simulation	en_US
DC.type	博碩士論文	zh_TW
DC.type	thesis	en_US
DC.publisher	National Central University	en_US