博碩士論文 945401004 完整後設資料紀錄

DC 欄位 語言
DC.contributor電機工程學系zh_TW
DC.creator李宇軒zh_TW
DC.creatorYu-Hsuan Leeen_US
dc.date.accessioned2010-7-27T07:39:07Z
dc.date.available2010-7-27T07:39:07Z
dc.date.issued2010
dc.identifier.urihttp://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=945401004
dc.contributor.department電機工程學系zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstract在現今的液晶顯示系統中,其功能主要可以分為三個部分,第一部份是streaming part,其最主要的目的在於處理多元化的視訊輸入資料,而第二部分是Digital TV part,它的主要功能在於image scaling、color enhancement及色彩飽和度的加強等,第三部分是LCD panel control part,它負責將所要顯示的資料依據LCD的既定的驅動格式,傳送至LCD panel進行顯示。而在未來的發展趨勢中,顯示畫面顯示率(frame rate)及畫面的解析度(display resolution),都會一致性的往高階應用來發展,這也造成在系統中用於儲存畫面的記憶體(frame memory)及記憶體頻寬(memory bandwidth)大幅增加,因此本論文針對此點提出一個嵌入式壓縮(embedded compression, EC)核心設計來提高系統對於記憶體的使用效率,可分為下列三個部分討論。 首先我們提出VLSI-oriented FELICS演算法,其主要專注在Lossless的應用,此演算法包含simplified adjusted binary code和storage-less Golomb-Rice code,除此之外,針對色彩信號提出color difference pre-processing來增進編碼效率。我們以CMOS 0.13-um來來實現此編碼晶片,其最高throughput可達4.36Gbit/s,支援Full-HD(1920x1080)@60Hz於全彩信號的處理。 在第二部分,我們進而拓展至Losslesss/Near Lossless範疇,主要包含下列技術:(1). associated geometric probability model (AGPM). (2). content-adaptive Golomb-Rice code. (3). geometric-based binary code. (4). rate control mechanism. 以上四項技術主要是考慮到硬體架構設計效能並且兼顧編碼效率,因此在架構設計上,此架構能夠完全的應用pipelining data scheduling及parallel processing技巧來提升硬體執行效率,因為資料相依性的問題已在演算法設計上解決,由實驗結果可以顯示,其編碼效率勝過以快速編碼著稱的FELICS演算法,且僅和編碼效率較好,但演算法複雜度較高的JPEG-LS僅有平均6.17%的差異,除此之外,本演算法的運算資源消耗只需FELCS及JPEG-LS的43%。在硬體效能方面,整個編解碼晶片是以TSMC 0.18-um 1P6M製程和Artisan cell library所建構而成,在雙倍平行的架構下,其最高吞吐率可達 6.4 Gbit/sec,core size為1.82x1.80 mm2,die size為2.33x2.30 mm2,其中logic gate count佔45.30K,on-chip memory使用量是3.8K Byte. 其編解碼處理能力可以完全涵蓋QFHD (3840x2160) @ 30Hz,可藉由multi-level拓展至120Hz的應用上。 第三部分,我們提出一個針對視訊編解碼器的EC演算法,其主要的技術內容涵蓋了ABC-based recompression,side clipping mechanism及average-based prediction。此演算法在2倍的指定壓縮效率(Target compression ratio, TCR)之下,其平均對於PSNR的損耗僅有1.37dB,其運算複雜度對於整體編碼運算而言,僅有平均2.4%的負擔,因此,其非常適用於現今的視訊編碼解系統應用上。 zh_TW
dc.description.abstractThe modern LCD display system can be categorized into three parts: streaming part, digital TV part and LCD panel control part. All three parts exhibits two common features: computation-intensive and bandwidth-intensive. With the rapid progress of semiconductor industry, the computation-intensive issue can be properly handled by parallelism or pipeline processing. Therefore, bandwidth-intensive issue becomes more and more important in this system. The embedded compression (EC) technology is widely applied to save frame memory size and bandwidth requirement. In lossless EC scenario, the VLSI-oriented FELICS algorithm, which consists of simplified Adjusted Binary Code and Golomb-Rice Code with storage-less k parameter selection, is proposed to provide the lossless compression method for higher throughput applications. Besides, the color difference pre-processing (CDP) is also proposed to improve coding efficiency with simple arithmetic operation. Based on VLSI-oriented FELICS algorithm, the proposed hardware architecture features compactly regular data flow, and two-level parallelism with four-stage pipelining is adopted as the framework of the proposed architecture. The chip is fabricated in TSMC 0.13-um 1P8M CMOS technology with Artisan cell library. The maximum throughput can achieve 4.36 Gbit/sec. In lossless/near lossless EC scenario, the proposed high-speed EC algorithm comprises three features: (1) The associated geometric-based probability model (AGPM) is developed to construct context-modeling mechanism without context-table. (2) Develop content-adaptive Golomb-Rice code and geometric-based binary code as the entropy coding with minor order of context. (3) Provide the rate control mechanism to guarantee the saving ratio of memory bandwidth and capacity. The entire codec chip is implemented in TSMC 0.18-um 1P6M CMOS technology. The maximum throughput is as high as 6.4 Gbit/sec. Furthermore, with multi-level parallelism, the performance can be extended to QHD (2560x1440)@120Hz and QFHD@120Hz for double frame rate (DFR) technique. For video coding system, an efficient EC algorithm, including ABC-based recompression, side-clipping mechanism and average-based prediction, is proposed. With proposed EC algorithm, the compression ratio (CR) of 50% can be guaranteed with minor PSNR loss of 1.37db on average. Although EC is an additional function in video coding system, the extra encoding computation load is just 2.4% on average. Consequently, the proposed EC algorithm can be exploited to reduce the frame memory and bandwidth requirement in video coding systems. en_US
DC.subject內容模型zh_TW
DC.subject嵌入式壓縮zh_TW
DC.subject超大型積體電路架構zh_TW
DC.subject位元率控制zh_TW
DC.subject無失真/近似無失真壓縮zh_TW
DC.subjectVLSI architecture.en_US
DC.subjectlossless/near-lossless compressionen_US
DC.subjectrate controlen_US
DC.subjectEmbedded compression (EC)en_US
DC.subjectcontext-modelingen_US
DC.title適用於液晶顯示系統之嵌入式壓縮演算法 及其晶片架構之設計與實現zh_TW
dc.language.isozh-TWzh-TW
DC.titleDesign and Realization of Embedded Compression Algorithm and VLSI Architecturefor LCD Display System en_US
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

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