| dc.description.abstract | Thanks to the rapid advance in the technologies of integrated circuit (IC) during the last ten years, it is possible to realize a complex signal process system with large number of transistors in a single microchip, which creates the possibility of reconstructing lost sophisticated human sensations. Today, implantable chips, such as the cochlear implant, have been able to be used to regain the greater part of the sense of lost hearing. Visual prostheses have been considered potential cure for people who suffer from blindness. Though such prostheses have been extensively studied over the decade, there are, however, still many bottlenecks that need to be overcome prior to actual application. This dissertation aims for accomplishing an efficient system for visual prostheses. While the designs presented in the dissertation are mainly for such applications, they are easy to be applied to other similar systems with different prosthetic purposes, with only minor modification of the system.
With regard to the contents of the dissertation, first of all, an ASK demodulator architecture capable of dealing with most of the previous limitations in an ASK-utilized medical implant, especially in want of being powered through wireless delivering, is proposed. It features the abilities of working on a very small modulation index and being provided without any R/C component(s) inside by means of a self-sampling scheme. Implemented in a 0.18-μm CMOS process, the demodulator occupies a die size of merely 32.3×14.5 (um×um). Analytic results from both simulation gradation and measurement phase show that the proposed circuit can operate at carrier frequency of 2 MHz and achieve a modulation rate of up to 50% when tested under an experimental set-up using signal generator. The average power consumption is in the vicinity of 336 uW. The results also indicate that the presented work can still perform a proper demodulation even with a modulation index is beneath 5.5%.
Second, a fully integrated energy-aware wirelessly powered prosthetic system architecture based on adiabatic switching has been developed. The proposed architecture can allow up to 40 frame/sec with 240 stimulus channels in mode I and three times the resolution at the same frame rate in mode II under a carrier frequency of 2 MHz, suitable for the multi-channel prostheses requiring real-time scanning such as visual prostheses. To cater to higher spatial resolution in sensation, the prototypical system has been constructed with a 16-channel-based stimulation scheme so that the design can be extended toward various experimental requirements. Fabricated in a
0.18-um CMOS process, the proposed prosthetic system has an 80% reduction in BER of the demodulated data and 18% saving in the average current consumption of the extraocular platform as compared with those designed in the conventional (non-energy-recovery) baseband architecture, showing the potential of the proposed system in improving overall system efficiency in spite of the weakness of the considerably increased fail-bit rate in other parts of itself. The increased fail-bit rate is mainly associated with the intrinsic dead zone in the logic evaluation in the employed energy recovery technique.
In response to the weakness, the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families were conducted and are presented in the third part of the dissertation. The newly developed ERL inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. It also features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required. This yields considerable improvements in area and power overheads as a whole. Moreover, the throughput of the newly developed energy recovery logic becomes twice as high as that of QSERL when tested with the same frequencies of power clocks. Comparison between the proposed logic style and other known logic style achieving iso-performance, namely, subthreshold logic is given. To demonstrate the workability of the proposed logic style, an 8-bit shift register, designed in the proposed logic style, has been fabricated in the 0.18-um CMOS process. Both simulation and measurement results verify the functionality and advantages of the proposed logic, suggesting that it is suitable for implementing performance-efficient and energy-aware very-large-scale integration (VLSI) circuitry and being used in the energy-aware electronic prosthetic system to cope with the choke point mentioned above namely the increased fail-bit rate.
In the last part of the dissertation, two techniques are presented to further enhance the system efficiency. The first is an efficient phase-shift keying demodulator (PSKD) featuring low power, low cost, and truly low-complexity implementation. By taking advantages of a high signal-to-noise ratio on wirelessly power-combined data transmission, the demodulation of the BPSK signal can be performed without the complex carrier recovery circuits requiring phase-locked loop (PLL). The proposed PSK demodulator, the circuit schematic of which has been fabricated in the 0.18-um CMOS process, recovers a binary data rate with up to 800 Kbps while consumes power less than 59 uW when tested in a real wireless-link setup. The second refers to a fully integrated low-loss CMOS rectifier. By making use of high-performance active diodes fulfilling almost ideal switching (zero forward voltage drop) and circuit to be provided with negative resistance, the proposed design is able to achieve a maximum of more than 90% conversion efficiency when fabricated in the 0.18-um standard CMOS process and tested in a real wireless link, without any special device requiring additional manufacturing procedures. The design considerations along with the proposed system and each of the key building block techniques will be detailed in the dissertation. | en_US |