| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 郭晉誠 | zh_TW |
| DC.creator | Chin-Cheng Kuo | en_US |
| dc.date.accessioned | 2009-7-15T07:39:07Z | |
| dc.date.available | 2009-7-15T07:39:07Z | |
| dc.date.issued | 2009 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=945401022 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著元件尺寸的遽縮，奈米製程使得單晶片(SOC)設計的應用越來越普遍。在這類混合訊號(analog/mixed-signal)的設計中，整合數百萬個邏輯閘來做系統驗證的困難度日益增加。此外，製程變異(process variation)與電源雜訊(supply noise)大幅地影響電路效能，進而造成良率的下降，對於敏感的(sensitive)類比電路來說，其影響更加的劇烈。因此，良率導向設計(design-for-yield, DFY)在近年來非常的熱門，其概念是希望在電路的設計初期，就把可能發生的環境變異因素考慮進來，減少重新設計(re-design)、再次光罩(re-spin)的時間與成本。
本論文提出一套有效率的參數萃取流程，針對鎖相迴路(PLL)電路，建立由下往上(bottom -up)的類比行為模型(analog behavioral model)。這樣高階層的模型擁有不錯的精準度，因此能夠取代現有電路來做快速的系統驗證。此外，在電源雜訊的考量下，我們擴充這個行為模型的功能，能將雜訊對電路效能的影響反映出來。同時，針對鎖相迴路建立其等效的狀態控制電阻(state-controlled-resistors)之巨集模型(macromodel)，這樣的概念不但能處理雜訊交互影響的問題，還能與其他考慮電源雜訊(supply-noise-aware)的模型整合在一起，在高階層、快速分析的優勢下，預估出接近實際系統的雜訊波形，並且評估雜訊對鎖相迴路效能的影響。
至於元件參數變異(device parameter variation)的影響，本論文提出了行為階層蒙地卡羅模擬(Behavioral Monte Carlo Simulation)的概念，利用行為模型來做統計分析、評估製程變異下的設計良率(design yield)。如果良率結果不盡理想，本論文在最後提出一套創新的良率改進(yield enhancement)方法，不須耗時地找出合理區域(feasible region)的邊界，而是利用已知的良率分析結果，找出擁有最佳良率的電路設計參數。這樣的演算法，能與現有的類比合成軟體(analog sizing tool)做結合，進而達到良率導向設計之目的。
從實驗結果可以知道，高階類比行為模型對於混合系統的驗證速度，會有一定程度的幫助。此外，本論文以電源雜訊與製程參數變異為例，提出擴充模型的方法與流程，並證明此行為模型能夠在設計初期，就能把環境變異的影響考慮進來，快速分析電路效能的變動程度，甚至提供電路改進的方向。相信這樣的方法，能夠幫助設計者面對深次微米製程(deep-submicron)的挑戰，加快設計速度以及提升電路良率。
| zh_TW |
| dc.description.abstract | While CMOS sizes are shrinking rapidly, more and more ASIC applications adopt System-on-Chip (SOC) designs with nanometer technologies. Such analog/mixed-signal (AMS) designs with over million components lead serious integration issues during system verification. Moreover, in real environment, variations on device parameters and supply voltage can strongly influence the circuit performances and design yield, especially for sensitive analog designs. Therefore, design-for-yield (DFY) techniques have recently become popular researches to solve the yield loss issues before manufacturing. Evaluating the variation effects on analog circuit performances at early design stages can help designers improve the design yield and reduce re-design cycles and re-spin cost.
A novel extraction flow is presented first in this dissertation to generate accurate behavioral models for PLL designs. Such bottom-up PLL model is accurate enough to replace the existing PLL intellectual property (IP) for system verification. For supply noise issues in AMS systems, a supply-noise-aware behavioral model is proposed in this dissertation to reflect real-time supply noise effects on PLL performances. Moreover, a simple SCORE (state-controlled-resistors) macromodel for PLLs is also proposed to handle the noise interaction issues at high level. Combined with the noise-aware models, this approach can provide accurate results as in real system simulation.
Considering device parameter variations, Behavioral Monte Carlo Simulation (BMCS) approach is presented in the third part of this dissertation to estimate the design yield of a PLL efficiently. If the analyzed yield is not satisfied, a novel yield enhancement algorithm is also proposed to improve the nominal design at behavioral level. This approach can be combined with current sizing tools to enable a DFY flow for analog circuits.
The experimental results show that accurate PLL behavioral models and related applications indeed speed up the AMS system verification. Variations in real environment can be reflected on PLL performances efficiently and considered at early design stages. We believe that these approaches can help analog designers overcome the design challenges with deep-submicron technologies.
| en_US |
| DC.subject | 鎖相迴路 | zh_TW |
| DC.subject | 類比電路行為模型 | zh_TW |
| DC.subject | 電源雜訊交互影響 | zh_TW |
| DC.subject | 良率優化 | zh_TW |
| DC.subject | analog behavioral model | en_US |
| DC.subject | yield enhancement | en_US |
| DC.subject | supply noise interactions | en_US |
| DC.subject | PLL | en_US |
| DC.title | 考慮電源雜訊交互影響與良率優化之鎖相迴路行為模型建立方法 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Bottom-up PLL Behavioral Modeling for Supply Noise Interactions and Yield Enhancement | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |