| dc.description.abstract | This thesis embraces two different themes. The first is the improvement in adiabatic logic for low-power design. The other is on the design of an efficient static random access memory (SRAM).
With reference to the first part, a structure called complementary energy path adiabatic logic (CEPAL) is proposed to improve the insufficiency of quasi-static energy recovery logic (QSERL). CEPAL employs respectively one additional transistor in its charging / discharging paths, compared to the QSERL counterpart, such that it can be with complementary energy paths. In addition, two complementary sinusoidal power clocks are used to achieve static CMOS characteristics. The two sinusoidal clocks do not require complex clocking schemes. CEPAL shortens substantially the time with respect to output floating, and has better fault tolerance, static noise margin, driving ability, and tolerance to process variation than QSERL.
In addition to the presented logic style, CEPAL was further applied to D flip-flop that is essential to the sequential circuits. We studied the properties of interest by means of a 0.18-um CMOS process. The CEPAL DFF achieves an energy saving of 60% compared to its QSERL counterpart when operating at 25 MHz. With the proposed share scheme, the two logic styles can have the same area cost in terms of the designed circuits.
As for the design of the SRAM, cell, write circuit and sense amplifier are of major improvement. In this part, we first propose to vary the cell aspect ratio so as to improve its static noise margin. We then propose to reduce the power loss during the write operation through shrinking the voltage swing on writing in data. Notably, we improve the sensing speed on read through using “equalizing” in place of the “precharging” in bit lines.
We have designed and simulated a 4-kb SRAM using Cadence environment and Hspice. Simulation results show that while the designed 4-kb SRAM is set up at 1-GHz clock and nominal 1.8-V DC power supply, the 8-bit data outputs can have up to 500-MHz speed, with a total power consumption (including the output buffers) of 8.932 mW. The designed SRAM has been fabricated through the National Chip Implementation Center (CIC), Taiwan, R.O.C.. | en_US |