| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 蘇芳瑩 | zh_TW |
| DC.creator | Fang-Ying Su | en_US |
| dc.date.accessioned | 2008-1-23T07:39:07Z | |
| dc.date.available | 2008-1-23T07:39:07Z | |
| dc.date.issued | 2008 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=945901004 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 半導體製程不斷進步，超大型積體電路的晶片整合系統(System-on-Chip, SOC)已成趨勢。當系統整合於同一晶片中，系統同步時脈訊號更顯重要，鎖相迴路(Phase-Locked Loop, PLL)或延遲鎖定迴路(Delay-Locked Loop, DLL)是常用的時脈產生器，然而時脈抖動對於鎖相迴路以及延遲鎖定迴路而言是重要的參數。過去時脈抖動多由外部儀器量測，但由於鎖相迴路的操作頻率不斷提高，欲達到較高量測效能，將會相對的提高外部儀器成本，再加上外部儀器的探針會引入雜訊，影響量測結果，因此內建時脈抖動量測電路較適用於PLLs量測。
本論文提出之時脈抖動量測電路為改良式脈衝縮減延遲電路，而傳統的電路「具高解析度之循環式時間至數位轉換器」[1]是以不同尺寸比例的反相器達到脈衝縮減，而本論文將原本單一路徑之縮減元件改為雙路徑，以的上升下降時間的不匹配達到相同的脈衝縮減效果。然而為了使量測電路之解析度更加精確，於是在脈衝縮減元件加上兩組補償電路，分別為電壓抖動補償電路與製程偏移補償電路。
本論文以CMOS 0.18um 1P6M製程來實現，電路的工作電壓為1.8V。電路操作頻率1GHz，電路解析度為5ps，消耗功率為1.7mW。含I/O pad的晶片總面積為753um × 592um，核心電路部份面積為108um × 59um。 | zh_TW |
| dc.description.abstract | As the improvement of semiconductor technology, the current trend of VLSI circuit is System-on-Chip (SOC). When many systems were integrated into a chip, the system synchronization clock signal must be accurate. We usually choose Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL) as the reference clock generator. However, the jitter characteristic of the PLLs or DLLs is the most important parameter. In the past, the jitter was measured by the external equipment. But, with the increased operating frequency, it has a higher cost on jitter measuring by external equipments. Moreover, sometimes probes of external equipments will induce noise, then the measurement result is disturbed. In view the problem, the built-in jitter measurement circuit is adapted to the PLLs.
In this thesis, an improved pulse shrinking delay element for clock jitter measurement is proposed. The traditional cyclic CMOS time-to-digital converter circuit [1] was changed the size of inverters to complete pulse shrink. We use two path with differential rising time and falling time to achieve pulse shrink. In order to make the measurable circuit have high accuracy, the compensated circuit is added to compensate the voltage and process variation.
The proposed circuit is designed in CMOS 0.18um 1P6M process. The operation voltage is 1.8V in the circuit. The reference frequency is 1GHz and the resolution of measurement circuit is 5ps. The power consumption is 1.7mW
at 1GHz. Area with I/O pad in the chip is 753um × 592um, and the area of core circuit is 108um × 59um. | en_US |
| DC.subject | 電壓補償 | zh_TW |
| DC.subject | 製程補償 | zh_TW |
| DC.subject | 抖動量測 | zh_TW |
| DC.subject | 脈衝縮減 | zh_TW |
| DC.subject | process compensation | en_US |
| DC.subject | voltage compensation | en_US |
| DC.subject | jitter measurement | en_US |
| DC.subject | pulse shrinking | en_US |
| DC.title | 改良式脈衝縮減元件用於時脈抖動量測 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | An Improved Pulse Shrinking Delay Element for Clock Jitter Measurement | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |