博碩士論文 953303009 完整後設資料紀錄

DC 欄位	值	語言
DC.contributor	機械工程學系在職專班	zh_TW
DC.creator	鄭英宗	zh_TW
DC.creator	Ying-Tsung Cheng	en_US
dc.date.accessioned	2012-7-18T07:39:07Z
dc.date.available	2012-7-18T07:39:07Z
dc.date.issued	2012
dc.identifier.uri	http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=953303009
dc.contributor.department	機械工程學系在職專班	zh_TW
DC.description	國立中央大學	zh_TW
DC.description	National Central University	en_US
dc.description.abstract	電漿技術在半導體製程中廣泛被應用，例如乾式蝕刻(dry etching)、薄膜沈積、去光阻等等都與電漿技術相關。隨著半導體工業的技術的進步積體電路的尺寸越做越小，所以蝕刻製程是否能精準完成微影中預定圖案轉移，為一個重要的製程。本論文中先在 TEL DRM機台內使用八氟環丁烷(C4F8)、三氟甲烷(CHF3) 、氯氣(Cl2) and溴化氫(HBr)等氣體來進行氧化矽與鍺金屬電漿蝕刻，研究其蝕刻率、均勻度與電漿蝕刻設備參數的關係。 再利用這些機台製程參數來開發出一種新型鍺全包覆式閘極電晶體元件(Ge Gate-All-Around FETs)，並藉由蝕刻技術來達到消除界面失配差排(Misfit dislocations)，或結合反覆式退火(Cyclic thermal annealing)，進ㄧ步降低線差排 ( Threading dislocations )，使之達到高品質鍺懸浮單晶結構，根據此結構可製作具有極佳閘門(Gate)控制和電性表現的新型鍺全包覆式立體結構閘極電晶體。	zh_TW
dc.description.abstract	A novel process to etch away the dislocated Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by gate all around with larger effective width (Weff) as compared to rectangular fin, and have good isolation due to nothing between Ge channel and SOI as well as the valence band discontinuity to keep holes away from Si at source and drain. By dislocation removal, the defect-free Ge channel can be formed on nothing. The device process is also expectedly applicable for bulk FinFET on nothing with similar performance.	en_US
DC.subject	鍺	zh_TW
DC.subject	乾式蝕刻	zh_TW
DC.subject	全包覆式元件	zh_TW
DC.subject	環繞式閘極電晶體	zh_TW
DC.subject	GeSi	en_US
DC.subject	Gate-All-Around	en_US
DC.subject	GAA	en_US
DC.subject	Dry etching	en_US
DC.title	透過乾式蝕刻製作新型鍺全包覆式閘極電晶體元件	zh_TW
dc.language.iso	zh-TW	zh-TW
DC.title	Dry etching process for Ge Gate-All-Around FETs on Si manufacturing	en_US
DC.type	博碩士論文	zh_TW
DC.type	thesis	en_US
DC.publisher	National Central University	en_US