| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳俊方 | zh_TW |
| DC.creator | Jiun-fang Chen | en_US |
| dc.date.accessioned | 2008-11-6T07:39:07Z | |
| dc.date.available | 2008-11-6T07:39:07Z | |
| dc.date.issued | 2008 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=955201018 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | D類放大器以其高效率及低功耗的優點，已被廣泛地應用於音訊產品上面。然而，傳統利用脈衝調變技術的D類放大器在三角波轉換成脈波訊號的過程中常伴有線性度的問題，造成D類放大器還原出來的音訊訊號品質較差。為改善此一問題，本論文採用用於高解析度的類比和數位資料轉換器電路上面的三角積分調變技術來設計D類放大器電路。此類三角積分調變D類放大器可避以免非線性的問題，且其利用雜訊移頻技巧可以抑制頻寬內的雜訊，提升效能。
針對D類放大器的電路設計，本論文將探討輸出級所包含的類比非理想的成份，包含訊號調變效應、輸出級後的波形失真、與輸出級供應電壓源的雜訊等等對系統效能造成的影響。本論文所設計的三角積分調變D類放大器電路,包含一個四階的三角積分調變器，超取樣率為64，工作頻率為2.56MHz。為降低D類放大器非理想效應對電路的影響，此電路採用閉迴路機制，以全差動交換電容式電路架構設計來實現。電路方面則是透過TSMC 0.18um製程來實現。系統在工作頻率2.56M、供應電壓3.3V、最大功耗1W及負載為4ohms的條件下，模擬結果可知，採閉迴路機制的D類放大器較開迴路機制而言，更能夠有效的改善訊雜比20dB。 | zh_TW |
| dc.description.abstract | Class D audio amplifiers have been widely used in audio applications for their high efficiency and less power dissipation. However, traditional pulse width modulation (PWM)-based class D amplifiers suffer from the linearity problems when converting pulse signals, causing poor quality for reconstructed output waveform. In this thesis, the class-D audio amplifier is designed with the sigma-delta modulation techniques used in high resolution data converters and is called as sigma-delta class-D amplifiers. By performing oversampling and noise shaping, the sigma-delta class-D amplifier can avoid the non-linearity problem and suppress the in-band noise
To fulfill the class-D amplifier circuit design, this thesis analyzes the influences of analog non-idealities at the output stage, including modulation errors, nonlinear errors in timing and shape of the output waveform, and the noise on power supplies. The designed class-D amplifier is with a closed-loop, forth-order sigma-delta modulator, an oversampling ratio of 64, and an operating frequency of 2.56MHz. The circuit is implemented with fully differential switch-capacitor circuitry and is with TSMC 0.18um process. Simulation results show that the closed-loop class D amplifier (with the operating frequency: 2.56MHz、supply voltage: 3.3V、power dissipation: 1W and load: 4ohms) can be improved 20dB SNR compared to the open-loop circuit. | en_US |
| DC.subject | 三角積分調變器 | zh_TW |
| DC.subject | D類放大器 | zh_TW |
| DC.subject | Class-D Amplifier | en_US |
| DC.subject | Sigma-Delta Modulator | en_US |
| DC.title | 交換電容式三角積分D類放大器電路設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of a Switched-Capacitor Sigma-Delta Class-D Amplifier | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |