dc.description.abstract | Modern system-on-chips (SoCs) typically encompass several hundreds of random access memory
(RAM) cores designed with aggressive design rules. Those memory cores usually represent
a significant portion of the chip area. Therefore, the yield of memory cores has heavy
impact on the SoC yield. Effective yield-enhancement techniques for those memory cores
thus are imperative. Built-in self-repair (BISR) technique has been widely used to repair
the memory cores in SoCs. Since a large amount of RAMs are distributed in a SoC, how to
boost the repair efficiency, minimize test and repair time, and minimize area cost of BISR
circuits is an important issue.
In the first part of this thesis, a high-repair-efficiency BISR scheme (HRE-BISR) is proposed.
The HRE-BISR reuses a local bitmap to serve as redundancy elements in normal mode
such that it can repair more faults. First, a HRE-BISR scheme reusing the local bitmap as
spare bits (HRE-BISR-SB) is presented. In addition, a row/column/bit redundancy analysis
algorithm is proposed to allocate redundancies of a RAM with the HRE-BISR-SB scheme.
Simulation results show that the proposed HRE-BISR-SB scheme can provide 0.48%–11.95%
increment of repair rate than a typical BISR scheme without reusing the local bitmap as
spare bits for different fault distributions. Secondly, a HRE-BISR scheme reusing the local
bitmap as spare words (HRE-BISR-SW) is presented, which can provide 0.71%–5.55% increment
of repair rate than a BISR scheme without reusing the local bitmap as spare words.
Finally, a minimal redundancy configuration searching algorithm is proposed to find a redundancy
configuration with minimal area cost for a RAM with HRE-BISR scheme under
a targeted repair rate.
In the second part of this thesis, a repair-rate-driven test scheduling technique is proposed
to minimize the test and repair time of RAMs with BISR circuits under the constraint of
maximum power consumption. An efficient test scheduling algorithm based on the earlyabort
probability calculated according to the repair rate is proposed. Simulation results show
that the proposed algorithm can achieve smaller test and repair time than existing works.
For ITC’02 benchmarks, for example, about 10.7% average reduction of expected test and
repair time can be achieved by the proposed algorithm.
In the third part of this thesis, a memory BISR planning (MBiP) framework is proposed
to plan shared BISR schemes for the RAMs in a SoC. The MBiP framework consists of a
memory grouping algorithm to select RAMs which can served by a shared BISR circuit.
Then, a BISR scheme allocation algorithm is proposed to allocate different shared BISR
schemes for the RAMs under the constraints of the results of memory grouping and a test
scheduling. Simulation results show that, about 22% area reduction can be achieved by
the proposed MBiP framework for 50 RAMs under 1.5mm distance constraint and 350mW
test power constraint in comparison with a dedicated BISR scheme. Finally, we extend the
MBiP framework to support the planning of shared BISR schemes for RAMs in SoC dies of
three-dimensional ICs by considering the constraints of pre-bond and post-bond test power
constraints. Simulation results show that 35% area reduction can be achieved by the shared
BISR scheme planned by the proposed planning technique under 1mm distance constraint,
500mW pre-bond test power, and 600mW post-bond test power constraints in comparison
with a dedicated BISR scheme. | en_US |