| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃健智 | zh_TW |
| DC.creator | Chien-Chih Huang | en_US |
| dc.date.accessioned | 2008-7-14T07:39:07Z | |
| dc.date.available | 2008-7-14T07:39:07Z | |
| dc.date.issued | 2008 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=955201033 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 進入深次微米的時代後，製程解析度快速縮小到比光學微影技術的光波波長還小時，製程的誤差將會越來越顯著且含有許多統計分佈的特性。伴隨著製程變動已被觀察到存在著空間相關性，因此，我們提出一套設計流程並應用於交換電容式的ΔΣ調變電路中的電容排列，此流程包含 1) 萃取各電容彼此的相關性 2) 依其相關性來決定各電容在實體佈局上的相對位置 3) 結合良率分析於實體佈局的決定。最後，發展為自動化設計平台可提供使用者良善的使用介面與降低設計上的複雜性。 | zh_TW |
| dc.description.abstract | The process variations increase with the advance of semiconductor manufacturing, and consequently influence the circuit parameters. Due to the device dimensions shrinking and the wafer sizes increasing, the intra-die variations are becoming dominant and strongly layout dependent. In this work, the correlations with each design parameters are extracted firstly and they are used as the guideline for layout placement. A flow procedure is proposed for determining the corresponding positions for each target parameters, which are implemented by the conjunctions of proper number of units. Experimentally, the procedure is applied to the placement of capacitances for switching-capacitor sigma-delta modulators. The result shows that the circuit yield can be enhanced further more by considering the correlation into placement. For analog and mixed-signal circuits, an automatic layout platform can greatly reduce the design complexity, in turn, speed-up the time spent for iteration, and further improve the yield. | en_US |
| DC.subject | 自動化 | zh_TW |
| DC.subject | 良率分析 | zh_TW |
| DC.subject | Automatic Layout Placement | en_US |
| DC.subject | Yield | en_US |
| DC.title | 應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Yield-aware Automatic Layout Placement via Capacitance Correlation for Switching-Capacitor Sigma-Delta Modulators | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |