| dc.description.abstract | This work demonstrates photodiodes (PDs) fabricated by standard silicon process technologies. Two kinds of PDs are proposed. One is in 0.35 um CMOS technology and the other is in 0.18 um CMOS technology.
This first section is the design of a high responsivity PD, and the PD layout is hexgon and ocagon in 0.35 um CMOS technology. The main ideas behind the layout design are to in crease the sidewall depletion region by fractal geometries. We show a good PD responsivity, the measured of the hexagon PD is 0.121 A/W and -3 dB bandwidth 790 MHz.
The second section is the design of a high bandwidth PD in 0.18 um CMOS technology. We remove the slow diffusion carries which are generated from substrate in CMOS PD by using body contact design with supplied voltage to curries into ground and improving PD bandwidth. When Body voltage is 10 V, the PD shows a much higher electrical bandwidth of 1.5 GHz.
In final section, we try to combine the Regulated Cascode Transimpedance amplifier (RGC TIA), Limiting amplifier(LA), and the previous available photodiode in Silicon (Si) CMOS technology to realize a high speed and highly integrated photoreceiver, which is fully compatible in standard Si CMOS process. Using Regulated Cascode Transimpedance amplifier at input can reduce effect of capacitance on PD and PAD. However, the voltage of the buffer stage is not considered carefully, hence the circuit gets a wrong current. The measured -3dB bandwidth of the differential and single-end circuit are about 2.2 GHz, and 1.4 GHz respectively, while their gain are about 49 dB and 52 dB.Implemented in a 0.18 um CMOS technology, the total power dissipation is 124 mW and 50.9 mW. The chip size is 0.6 mm2 and 0.576 mm2. | en_US |