| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 楊露瑜 | zh_TW |
| DC.creator | Lu-Yu Yang | en_US |
| dc.date.accessioned | 2008-7-25T07:39:07Z | |
| dc.date.available | 2008-7-25T07:39:07Z | |
| dc.date.issued | 2008 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=955201056 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在本論文中，利用低壓化學氣相沉積系統沉積複晶矽鍺並利用氧化之方式形
成鍺奈米晶粒製作出浮點電晶體，另一方面，我們以高介電層材料取代傳統的二
氧化矽做為穿隧介電層以提升寫入的速度;在製作浮點電晶體過程中，我們也開
發了閘堆疊蝕刻的部份，因為浮點電晶體閘堆疊層中的鍺奈米晶粒是否蝕刻乾淨
會嚴重影響元件的製作與特性。
我們利用製作出來的電晶體做了以下幾項的電性量測包含:室溫下儲存時間
量測、脈波量測、耐用性量測等，藉由以上的量測，我們可以清楚知道所製作的
元件之特性。 | zh_TW |
| dc.description.abstract | In this thesis, we utilize selective thermal oxidation of poly SiGe to form Ge
nanocrystals embedded in SiO2 and then fabricate the Ge nanocrystals transistor. In
addition, using high-K material to replace the conventional robust SiO2 enhances
programming speed. In the fabrication process, we have also developed the gate stack
etch technique, because of Ge nanocrystals embedded in gate stack has been removed
or not affects the following fabrications and characterization of device tremendously.
When the fabrication of device has been completed, we take some measurements
including, pulse response, endurance measurement and retention time at room
temperature. According to the result of measurements, we can realize the
characterization of our device and the problems of device structure | en_US |
| DC.subject | 非揮發性記憶體 | zh_TW |
| DC.subject | memory | en_US |
| DC.title | 應用氮化矽做為穿隧介電層之鍺量子點電晶體之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | the fabrication of Germanium nanocrystal MOSFET with SiN tunneling dielectric technology | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |