| dc.description.abstract | This doctoral dissertation focuses on the injection-locked oscillators for the microwave and millimeter-wave phase-locked loop (PLL). The basic concept of the injection-locked theory is introduced in Chapter 2. A phase noise model for the injection-locked oscillator (ILO) is proposed for the design and analysis. The output phase noise of the ILO is contributed from the injection signal with the lowpass response and the inherent noise of the ILO with the highpass response. The phase noise model of the ILO can be also applied to the sub-harmonically injection-locked PLL (SILPLL), injection-locked frequency divider (ILFD), and injection-locked frequency multiplier.
A W-band divide-by-three ILFD in 90 nm CMOS process is presented in Chapter 3. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W-Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power of the ILFD consumption is 1.5 mW with a supply voltage of 0.7 V. Furthermore, the proposed divide-by-three ILFD is also successfully integrated to a V-band PLL using 65 nm CMOS process. At an operation frequency of 58.5 GHz, the measured phase noise at 1 MHz offset is –83.5 dBc/Hz. The total dc power consumption of the PLL is 44 mW.
In Chapter 4, we proposed a W-band wide locking range injection-locked frequency tripler (ILFT) with low dc power consumption. By using a transformer coupled (TC) topology, the proposed TC-ILFT features the following advantages: 1) the negative resistance of the cross-coupled pair is not degraded due to the proposed TC-ILFT without source degeneration, and the TC-ILFT can be operated in lower dc supply voltage as compared to the conventional ILFTs, 2) the dc bias of the injector can be properly designed for maximizing locking range, 3) the parasitic capacitance provided by the injector can be reduced due to the impedance transformation, and 4) the larger device size of the injector can be chosen enhancing the third harmonic. Moreover, the operation frequency and the locking range are boosted using a multi-order resonator. A theoretical model of the proposed TC-ILFT is also established and it has been carefully verified with the experimental results. The free-running oscillation frequency of the proposed TC-ILFT is 94.51 GHz. As the input power is –1 dBm, the measured locking range is 5.9 GHz without varactor tuning. The dc supply voltage and the power consumption are 0.7 V and 1 mW, respectively.
A low jitter low phase noise 10-GHz SILPLL with delay-locked loop (DLL) self-aligned injection using 65 nm CMOS technology is presented in Chapter 5. With the proposed innovative topology, the phase between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator (SILVCO) in the PLL can be dynamically aligned to minimize the jitter over the variation. A theoretical model for the SILPLL is developed for the design methodology, and the in-band phase noise of the SILPLL can be significantly improved using the SIL technique. The design considerations of the locking range and frequency division ratio are addressed. As the operation frequency is 10 GHz, the measured phase noise of the proposed SILPLL with self-aligned injection is –130.2 dBc/Hz at 1 MHz offset with a rms jitter of 44 fs. The total dc power consumption is 62.7 mW.
Finally, the conclusion and future works are given in Chapter 6. | en_US |