| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃盟元 | zh_TW |
| DC.creator | Meng-yuan Huang | en_US |
| dc.date.accessioned | 2009-7-22T07:39:07Z | |
| dc.date.available | 2009-7-22T07:39:07Z | |
| dc.date.issued | 2009 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=955201103 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著半導體製程的縮小，製程變動的問題造成元件之間不匹配是日益嚴重。本論文提出Balanced-Via Channel Routing (BVCR)的繞線佈局法，可實現相關性電容的良率評估器所得到最佳佈局擺放，並依據既定的繞線方式達到所要求的元件匹配。BVCR遵照設計規則(Design rule)且著重於每個元件間的繞線的長度平衡。除此之外，BVCR的自動繞線機制可大幅降低佈局時間及人力成本，以加速產品上市的時效。
| zh_TW |
| dc.description.abstract | Devices mismatch is usually caused by the process variation. The uncontrollable process variation has become a severe problem as the semiconductor technology continues to shrink. We proposed the Balanced-Via Channel Routing (BVCR) to implement the optimum placement which generated by yield evaluator. Based on routing style of BVCR and design rules, the routing wires between devices can be balanced. Furthermore, the automatic system of BVCR can reduce the design costs and speed-up the time to market.
| en_US |
| DC.subject | 平衡接點之通道繞線法 | zh_TW |
| DC.subject | 良率評估器 | zh_TW |
| DC.subject | 空間相關性 | zh_TW |
| DC.subject | 共質心 | zh_TW |
| DC.subject | yield evaluator | en_US |
| DC.subject | Balanced-Via Channel Routing | en_US |
| DC.subject | Common -Centroid | en_US |
| DC.subject | Spatial Correlation | en_US |
| DC.title | 陣列MiM電容的平衡接點之通道繞線法 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Balanced-Via Channel Routing for Array-type MiM Capacitors | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |