| dc.description.abstract | With the progress and development of the world, it results in a great mount of natural resources use and the energy requirement and rapid consumption of the energy. Due to the limited natural resources, how to use the energy efficiently without wasting becomes an important question.
Power metal oxide semiconductor field effect transistor are used widely in a lot of fields includes consumer electronics, computers, communication, car electronics, and home appliances. Due to the energy saving, how to reduce the power loss becomes a target for devices designers. For low voltage power VDMOSFETs, it proposed wing cell design, combining the square cell and linear cell. The wing cell removes a part of the poly area between each cell. Therefore, both the channel density and current path can be increased. Consequently, the on-resistance can be reduced efficiently. The wing cell design can be used to the planar-gate and trench-gate power VDMOSFETs.
For high voltage power VDMOSFETs, the long gate length can not be avoided because the parasitic JFET resistance. Due to this reason, low switching speed and high switching loss occur. In order to decrease them, a split gate with floating np-well power VDMOSFET and overall implant power VDMOSFET are proposed. The split gate with floating np-well power VDMOSFET removes a part of gate area. However, the electric field crowding and high on-resistance were happened at the same time. Consequently, a floating np-well is incorporated to solve it. On the other hand, shortening the gate length is a more easy way to improve switching speed and switching loss. But, the parasitic JFET resistance increases rapidly with the shortened gate length. Therefore, a high concentration layer is required to restrain the parasitic JFET resistance while shortening the gate length.
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