| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林友正 | zh_TW |
| DC.creator | Yo-chen Lin | en_US |
| dc.date.accessioned | 2009-12-13T07:39:07Z | |
| dc.date.available | 2009-12-13T07:39:07Z | |
| dc.date.issued | 2009 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=965201001 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 摘要
隨著現代半導體製程技術進入深次微米時代，製程變動對於電路效能的影響越來越嚴重。因為製程變動已被觀察出存在空間相關性的緣故，我們需要高速且可考慮製程變動相關性的方法使我們可以更準確的估計電路效能參數的變動以減少設計疊代成本。我們提出一個可以計算類比電路各階層參數變異數之高速變異數分析法的延伸架構，使之能探討當製程參數存在相關性的情況，並利用實驗進行比較，實驗的結果顯示此分析器的精確度及效率皆相當出色。
| zh_TW |
| dc.description.abstract | Abstract
As technological scales down to ultra-deep-submicron, the impact of process variation on circuit performance gains importance. For it has been observed that the process variations are spatially correlated, analysis with consideration of process parameters correlations and high computational efficiency is needed to help estimating variations of circuit performance accurately and reducing the cost of design iteration. We present an extended scheme of prior high speed hierarchical variance analysis method to calculate the variances of parameters at each hierarchical layer in analog circuits while taking process parameters correlations into account. Experimental results show that the method achieves high computational accuracy.
| en_US |
| DC.subject | 階層式變異數 | zh_TW |
| DC.subject | An Extended Hierarchical Variance | en_US |
| DC.title | eHVA-II: 一個具功能模型的類比電路
延伸階層式變異數分析器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | eHVA-II: An Extended Hierarchical Variance Analyzerwith Functional Model for Analog Circuits
| en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |