| dc.description.abstract | Three-dimensional (3-D) integrated chip (IC) design technology is now widely acknowledged as one of the future chip design technologies. A 3-D IC has many benefits over a conventional 2-D IC, such as small form factor, high functionality, high performance, and low power consumption. Due to the regularity of a memory circuit, it is a very good candidate for 3-D technology. Content addressable memories (CAMs) are widely used in digital systems, such as networking, cryptography, compression, cache memory, etc. How to improve the performance and reduce the power of the CAM are two of key design issues. On the other hand, the area of a CAM cell is much larger than that of an SRAM cell because of that a CAM cell consists of a storage element and a comparator for executing parallel comparison. Therefore, if a large-capacity CAM is needed, then the footprint of the CAM is very large. 3-D integration technology can be used to reduce the power and the footprint of a large-capacity CAM.
In the first part of this thesis, three 3-D architectures for the CAM and priority address encoder (PAE) are proposed. The first is the Searchline-Partitioned 3-D CAM architecture (SPCAM3D), and the second is the Matchline-Partitioned 3-D CAM (MPCAM3D) architecture, and the third is the Searchline-Matchline Hybrid-Partitioned 3-D CAM (SMHPCAM3D). Moreover, a 3-D PAE with lookahead and folding techniques is introduced. Compared with the 2-D CAM architecture, simulation results show that the proposed SPCAM3D architecture with two 3-D layers gets about 29.13% improvement on search time when the number of words of the CAM is 1K; the MPCAM3D architecture with two 3-D layers gets about 23.21% improvement on search time when the word width of the CAM is 128; and the SMHPCAM3D architecture with four 3-D layers gets 66.78% performance improvement when the configuration of the CAM is 1K×128 bits. For the proposed 3-D PAE and 3-D folding PAE with two 3-D layers, simulation results show that they can provide 45.78% and 42.35% performance improvement, respectively, on critical delay time in comparison with the 2-D PAE if the size of PAE is 1K-bit. Finally, a reconfigurable CAM architecture for realizing a binary CAM or ternary TCAM is proposed. The reconfigurable CAM architecture can be implemented in a die as a binary CAM. On the other hand, one can stack multiple reconfigure CAM dies to realize a ternary CAM.
In the second part of this thesis, the comparison faults of ternary CAMs with asymmetric cells are defined first. Then, two march-like test algorithms are proposed to cover the defined comparison faults. The first test algorithm TACHit requires 8N Write operations and (3N+2B) Compare operations to detect 100% comparison faults for an N×B-bit TCAM with asymmetric cells and Hit output only. The second test algorithm TACHit requires 4N Write operations and (3N+2B) Compare operations to detect 100% comparison faults for an N×B-bit TCAM with asymmetric cells and Hit and PAE outputs.
In the last part of this thesis, test procedures for CAMs with the SPCAM3D and the MPCAM3D architectures are presented. A built-in self-test (BIST) scheme is proposed to test CAMs with SPCAM3D architecture. On the other hand, a BIST scheme is proposed to test CAMs with MPCAM3D architecture. Both the BIST schemes for 3-D CAMs can generate the March-like test algorithms for 2-D CAMs. The experimental results shows that the test time of 3-D BISTs for SPCAM3D and MPCAM3D are only 51.21% and 79.07%, respectively, of the test time of 2-D BIST.
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