| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃拓為 | zh_TW |
| DC.creator | To-Wei Huang | en_US |
| dc.date.accessioned | 2010-1-12T07:39:07Z | |
| dc.date.available | 2010-1-12T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=965201024 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在這篇論文中我們提出了一個Forth 多核心微處理器和在硬體上面運行的操作系統，我們用WHDVI系統命名它稱作做WHDVIForth，這個多核心微處理器執行聯合資源和通道編碼算法的程序。根據我們的系統，我們實現一個新的計算模型- 同時處理，它可以幫助我們在WHDVIForth設計在聯合資源和通道編碼的平行運算。我們發現WHDVIForth非常適合用在嵌入式系統，因為它夠小而且夠快，最後我們模擬和驗證我們的硬體在TSMC 0.18微米下，每個核心可以運行200 MHz，8.65k的等效邏輯大小，另一方面WHDVIforth的軟體是非常緊密的系統，大約5k位元組。
| zh_TW |
| dc.description.abstract | In the thesis, a new embedded forth multi-core microprocessor and its operation system, called WHDVIForth, are proposed. This multi-core microprocessor performs the procedures of the algorithm for joint source and channel coding. A kind of computation model, concurrent process, is implemented according to this system. WHDVIForth can be used to design joint source and channel coding algorithm. WHDVIForth also suits for embedded system since it is small and fast enough. Eventually, it is simulated and verified on TSMC 0.18um Cell-Based Design flow and it is running on 200 MHz with 8.65K gate count. On the other hand the system software is very compact, only about 5K bytes.
| en_US |
| DC.subject | 多核心微控制器 | zh_TW |
| DC.subject | multi-core micropocessor | en_US |
| DC.title | 嵌入式WHDVI多核心Forth微控制器之設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of an Embedded Forth Multi-core Microprocessor for WHDVI System | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |