| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 王裕淵 | zh_TW |
| DC.creator | Yu-yuan Wang | en_US |
| dc.date.accessioned | 2010-8-16T07:39:07Z | |
| dc.date.available | 2010-8-16T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=965201059 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文旨在探討利用兩種不同寬能隙的介電材料(氮化矽、二氧化矽)形成三層堆疊介電層以達到電致可調變穿隧能障之效，期望藉此可降低浮點電晶體的寫入與抹除之電壓，更可提升其寫入/抹除的效率。當閘極施予偏壓時，將使穿隧位能障產生近似對稱三角幾何的位能障來增加載子的寫入/抹除速度，並且利用低壓化學氣相沉積系統沉積複晶矽鍺並藉由濕氧化的方式形成鍺奈米晶粒的製程技術相結合實現出鍺浮點電晶體。本論文中是以氮化矽/二氧化矽/氮化矽堆疊所形成之穿隧介電層，其中的二氧化矽是在溫度為1050 oC 的環境下，以乾氧化氮化矽的方式所形成的。此製程方法能有效地控制穿隧介電層的等效氧化層厚度在5 nm 以下。且藉由不同寬能隙材料堆疊所形成對稱三角幾何的穿隧位能障，更能有效的降低元件的操作偏壓以及提升元件的操作速度與耐用性，又能保有元件的儲存能力。本實驗所製作而成的鍺浮點電晶體，寫入/抹除操作偏壓可降低至8 V 以及-6 V、操作速度分別可達到1 ms 以及70 μs，便可使得元件產生0.6 V 的記憶窗口。在儲存能力方面，儲存時間經過1E8 秒之後，儲存的電荷量尚保存原本的58 %。而在耐用性方面，元件的寫入/抹除操作次數可達到1E6 次以上。
| zh_TW |
| dc.description.abstract | In this thesis, we explored two wide bandgap insulators, silicon-dioxide and silicon nitride, as a stacked dielectric for forming a tunable tunnel barrier under electric-field modulation. The so-formed tunnel dielectric behaves like a symmetric quasi-triangle potential barrier, which is expected to enhance the read and write speeds for memory application. In addition, we also incorporate germanium quantum dots (QDs) to replace the floating poly-Si gate, so that a high speed and good charge retention Ge QDs flash memory is demonstrated.
The stacked tunnel dielectric of Si3N4/SiO2/Si3N4 is produced by thermally oxidizing amorphous Si3N4 at 1050 oC and its equivalent oxide thickness (EOT) is less than 5 nm. The so-formed stacked tunnel dielectric behaves like a quasi-triangle potential barrier under E-field manipulation. Incorporating Ge QDs with the quasi-triangle tunnel barrier into the MOSFET structure, we realized a floating-dot nonvolatile memory cell transistor with the write/read voltages of +8 V and -6 V, write/read time of 1 ms and 70 μs at a threshold voltage shift (ΔVTH = 0.6 V). This Ge QDs transistor have good charge retention of 58 % after 1E8 s and excellent endurance after more than 1E6 read/write operations.
| en_US |
| DC.subject | 鍺浮點電晶體 | zh_TW |
| DC.subject | 電致可調變穿隧能障 | zh_TW |
| DC.subject | 非揮發性記憶體 | zh_TW |
| DC.subject | E-field induced tunable tunnel barriers | en_US |
| DC.subject | nonvolatile memory | en_US |
| DC.subject | Ge floating dot transistor | en_US |
| DC.title | 應用氮化矽/二氧化矽/氮化矽堆疊形成電致可調變穿隧能障之鍺量子點電晶體之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Fabrication and Characterization of Germanium Quantum Dots MOSFET with Electric-field Induced Tunable Tunnel Barriers in Si3N4/SiO2/Si3N4 Stack. | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |