| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃正宇 | zh_TW |
| DC.creator | Zheng-Yu Huang | en_US |
| dc.date.accessioned | 2010-6-21T07:39:07Z | |
| dc.date.available | 2010-6-21T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=965201116 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文目標是針對4×4多輸入多輸出訊號偵測問題來設計和實現一個高吞吐量QR分解的硬體。實數轉換，通道矩陣被展開成8×8大小的矩陣。本論文提出一個QR分解方案，先以複數Givens rotation再以實數Givens rotation做QR分解運算，來取代一般直接轉換成實數矩陣並矩陣三角化的方式。在演算法的複雜度上可以減少44%的運算量。為了達到高吞吐量以及容易地管線化，採用systolic array架構來實現硬體。在傳統複數QR分解systolic array架構中，需要有許多延遲單元來讓資料能以歪斜的輸入方式。針對此問題加以改良，設計一個不用歪斜輸入的架構，同時減小硬體，移除約37%的延遲單元。在實數Givens rotation的部分採用堆疊的triangular systolic array架構來達到與複數級相同的產出速率，且以排程和分時多工技術改良在此部分的使用率及硬體大小。我們使用TSMC 0.18μm CMOS製程來實現此QR分解硬體，gate count為152K。根據晶片繞線佈局後的模擬結果，最大操作頻率可以達到90.09MHz，本論文提出的方案和硬體架構不僅減少了硬體複雜度，也可支援高吞吐量的多輸入多輸出訊號偵測器至2.16Gbps的傳輸速率。我們也探討在MIMO-OFDM系統中，沒有非同步問題之訊號偵測的效能。在OFDM系統中，QR分需要大量零散的記憶體，我們使用區域性緩衝器來合併並減少記憶體數量，利用此方式可增加記憶體的使用效率。
| zh_TW |
| dc.description.abstract | In this thesis, we aim to design and implement a high-throughput QR decomposition architecture for 4 ×4 MIMO signal detection problems. A real-value decomposed MIMO system model is handled and thus the channel matrix to be processed is extended to the size 8×8. Instead of direct factorization, we propose a QR decomposition scheme by cascading one complex-value and one real-value Givens rotation blocks, which can save 44% hardware complexity. The systolic array is adopted for hardware implementation to facilitate pipeline design. Then, the requirement of skewed inputs to the conventional complex-value QR-decomposition systolic array is improved and 37% of delay elements are removed. The real-value Givens rotation stage is implemented by a stacked triangular systolic array to match with the throughput of the complex-value one, and improve the hardware complexity using scheduling and time-sharing. We have implemented the proposed design in TSMC 0.18μm CMOS technology with 152K gates. From post-layout simulations, the maximum operating frequency can achieve 90.09MHz. The proposed scheme not only reduces the hardware complexity, but also supports high throughput for MIMO-OFDM signal detection up to 2.16Gbps under stationary channels. We also analyze the performance of MIMO detection with perfect synchronization in MIMO-OFDM systems. In this system, a lot of bitty and piecemeal memory of QR decomposition is required. We integrate all the small memory and improve the mount of memory at QR decomposition module by local buffers. With this technique, the efficiency of memory can be increased.
| en_US |
| DC.subject | QR分解 | zh_TW |
| DC.subject | 多輸入多輸出 | zh_TW |
| DC.subject | 正交分頻多工 | zh_TW |
| DC.subject | QR decomposition | en_US |
| DC.subject | OFDM | en_US |
| DC.subject | MIMO | en_US |
| DC.title | 適用於正交分頻多工系統多輸入多輸出訊號偵測之高吞吐量QR分解設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | High-Throughput QR Decomposition for MIMO Detection in OFDM Systems | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |