| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 張劭鍇 | zh_TW |
| DC.creator | Shao-kai Chang | en_US |
| dc.date.accessioned | 2010-11-18T07:39:07Z | |
| dc.date.available | 2010-11-18T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=965201126 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文提出一個快速的六十四位元加法器﹐使用動態的邏輯電路及傳輸閘的架構﹐應用於Brent-Kung Tree。此加法器為混合式的加法器架構，其採用前瞻進位單元和多工器且具有8個邏輯閘階層。由模擬結果顯示，混合加法器在最壞情況的延遲為298ps，而使用的製程技術為TSMC 0.18 um 2P6M CMOS technology，電源電壓為1.8伏特。同時我們也在其他的先進製程中模擬，模擬結果顯示，混合加法器在最壞情況的延遲為110ps，而使用的製程技術為UMC 90 nm 1P9M CMOS Low-K technology，電源電壓為1伏特。
| zh_TW |
| dc.description.abstract | The thesis presents a fast 64-bit adder based on domino logics and pass transmission gates in the Brent-Kung Tree. The proposed adder uses a hybrid adder of Carry Look-Ahead and MUX architecture in 8 logic levels. Simulation results show that the proposed hybrid adder achieves a delay of 298ps, where the TSMC 0.18 um 2P6M CMOS technology with the supply voltage of 1.8V. Based on UMC 90 nm 1P9M CMOS Low-K technology with the supply voltage of 1V, the proposed 64-bit hybrid adder achieves a delay of 110ps with 6mW power dissipation.
| en_US |
| DC.subject | 混合式加法器 | zh_TW |
| DC.subject | 前瞻進位加法器 | zh_TW |
| DC.subject | 跳躍進位加法器 | zh_TW |
| DC.subject | 平行預算加法器 | zh_TW |
| DC.subject | Parallel Prefix adder | en_US |
| DC.subject | Carry Skip Adder | en_US |
| DC.subject | Carry lookahead adder | en_US |
| DC.subject | Hybrid Adder | en_US |
| DC.title | 混合式加法器設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Hybrid Adder Designs | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |