| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系在職專班 | zh_TW |
| DC.creator | 趙盈勝 | zh_TW |
| DC.creator | Ying-shang Chao | en_US |
| dc.date.accessioned | 2011-11-30T07:39:07Z | |
| dc.date.available | 2011-11-30T07:39:07Z | |
| dc.date.issued | 2011 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=965301003 | |
| dc.contributor.department | 電機工程學系在職專班 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在類比/混頻電路(Analog/Mixed-Mode circuit)的先進製程中，為加快設計流程(Design Flow)與提高產品開發的成功率，設計者需直接使用晶圓代工廠(Foundry)提供之製程設計套件(PDK)做電路設計(Circuit design )、模擬(Simulation)與佈局(Layout)。製程設計套件(PDK)為晶圓代工廠，依該製程之特性並收集生產線上開發製程時，所累積經驗與整合使用者需求而來。製程設計套件(PDK)亦需晶圓代工廠與電子設計自動化 (EDA)廠商密切合作，以將各功能包裹進使用者使用之開發環境。
另在類比/混頻電路(Analog/Mixed-Mode circuit)中，我們常需考慮電路中，元件的匹配度問題以提高電路效能；但卻考慮不到，這些需高度匹配的元件在晶圓實際製程流程中，遇到的製程變動問題，可能降低元件匹配度。
故我們引入陣列區塊電容產生器(Array-Block-Capacitance Creator)，即以啟發式演算法(Heuristic Algorithm)做陣列區塊電容之佈置，再利用統計學之空間相關性模型(Spatial-Correlation Model)做評估，最後再藉設計製程套件(PDK)的開發流程，評量如何將其內建於現有設計製程套件(PDK)中，藉此提供類比/混頻電路(Analog/Mixed-Mode circuit)在設計佈局(Layout)時最佳解法。
| zh_TW |
| dc.description.abstract | In Analog/Mixed-mode advance process, designer need use Process Design Kit to speed up the design flow and to enhance the success of product development. “Process Design Kit” is provided and verified by Foundry, it included the properties of the specified process, collecting the experience while process development, and integrate user’s request. “Process Design Kit” needs closer cooperation within Foundry and EDA vendor.
In Analog/Mixed-mode circuit, we also need consider about the device matching to keep the performance of the circuit. But it’s not easy to predict and control the device matching while the devices in foundry’s process. Because the process variation affects the device character and reduces the device matching.
We use Heuristic algorithm to get the placements, and find-out the optimal placement by considering the spatial correlation model which comes from Statistic. These procedures provided us a good solution, “Array-Block-Capacitance Creator”. By qualified our solution within PDK provider’s development flow and user’s design flow, we could embedded and used it in current PDK.
| en_US |
| DC.subject | 陣列區塊電容產生器 | zh_TW |
| DC.subject | 製程設計套件 | zh_TW |
| DC.subject | Array-Block-Capacitance Creator | en_US |
| DC.subject | Process Design Kit | en_US |
| DC.subject | PDK | en_US |
| DC.subject | FDK | en_US |
| DC.title | 陣列區塊電容產生器於製程設計套件之評量 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Qualification of the Array-Block-Capacitance Creator for Process Design Kit | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |