| DC 欄位 |
值 |
語言 |
| DC.contributor | 資訊工程學系在職專班 | zh_TW |
| DC.creator | 王士銘 | zh_TW |
| DC.creator | Shih-Ming Wang | en_US |
| dc.date.accessioned | 2010-7-28T07:39:07Z | |
| dc.date.available | 2010-7-28T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=965302005 | |
| dc.contributor.department | 資訊工程學系在職專班 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在網路化嵌入式系統中，網路運算通常佔用處理器大量的計算資源。尤其在Gigabit等級以上的嵌入式網路系統，由於速度和功耗的問題，已不適合用嵌入式軟體的方式在MCU或DSP上實現。因此本研究致力於設計一個UDP/IP硬體加速器，以便有效降低系統的計算負擔並提升高速網路整體效率。
本論文採用MIAT嵌入式硬體方法論來設計UDP/IP硬體加速器，包含管線化的傳送及接收控制器以及可儲存一組連線的表格，連線資訊可以透過遠端以封包指令修改。系統先以IDEF0進行階層式模組化的分析，使底層的每一個模組皆可以獨立運作，並透過GRAFCET工具為每一個獨立的模組進行離散事件建模，再以VHDL硬體描述語言合成其硬體電路。我們於FPGA完成每個模組的功能性驗證。整體系統使用了1404個Logic Elements，傳送速度達 137.14 MB/s，接收速度為173.10MB/s，可滿足Gigabit的嵌入式網路應用系統的效能需求。最後搭配市售的Gigabit MAC與PHY進行嵌入式系統整合驗證和性能測試。本研究成果將來可以應用在高速的遠端視訊監控等網路多媒體應用或是高資料流的網路遊戲應用。
| zh_TW |
| dc.description.abstract | In networked embedded systems. Network computing usually takes a lot of computing resources of processor. Grade and above, especially in embedded Gigabit Network System, Because of the speed and power consumption issues, It is not suitable to use embedded software to achieve in the MCU or DSP. Therefore, this research is to design a UDP / IP hardware accelerator. In order to reduce the computational overhead and improve the system overall efficiency of high-speed network. In this thesis, we use MIAT methodology to design an embedded hardware UDP / IP hardware accelerator. Which including pipelined transmitter and receiver controllers, and a connection table which can store information of current connection. Connection information can be modified by instructions inside UDP package sent by remote side, First we analysis whole system with hierarchical modular IDEF0, each module can operate independently, then we perform discrete event modeling on each module by GRAFCET. Finally we write VHDL hardware description language code to synthesis GRAFCET into hardware circuit, we complete functional verification for each module in FPGA. The whole system uses a 1404 Logic Elements, transmit speed up to 137.14 MB/s, receive is 173.10MB/s. With a commercially available Gigabit MAC and PHY for Embedded system, we experiment the integration and performance verification test. The results of this study can be used in future high-speed remote video monitoring network multimedia applications or high data flow applications online games.
| en_US |
| DC.subject | 網路協定 | zh_TW |
| DC.subject | 協定加速器 | zh_TW |
| DC.subject | UDP加速器 | zh_TW |
| DC.subject | UDP offload engine | en_US |
| DC.subject | UDP/IP offload engine | en_US |
| DC.subject | offload engine | en_US |
| DC.title | Gigabit乙太網路的UDP/IP硬體加速器設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of UDP/IP Hardware Accelerator for Gigabit Ethernet | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |