dc.description.abstract | Since the advantage of CMOS technology satisfies the requirements of the low power consumption and high integration level in multi-GHz radio frequency (RF) transceiver designs, RF CMOS transceiver has been popularly applied in consumer products and wireless communications. Nowadays, the demand of green-power design mechanism in CMOS RF transceiver design becomes important, and the related research topics are listed as following. First, the design goals for low-power and low-voltage performances are always the critical issue to innovate for RF transceiver blocks. Conventional Gilbert cell mixer with three- cascode stages is difficult to keep all transistors operating in saturation region under low-voltage. The low-voltage operation requires modified circuit architecture, such as the folded-switch topology has been proposed to reduce the supply voltage and power consumption. Second, the passive device in CMOS process has high insertion loss which increases the power consumption to maintain circuit performance. The integrated passive devices (IPD) technology with glass substrate reduces the loss of substrate to improve the efficiency of RF circuits. The CMOS and IPD chips are assembled by flip-chip technology, which achieves high efficiency RF system-in-a-package (RF-SiP) wireless product. Finally, power amplifier (PA) is used to provide high output power to drive the antenna of a transmitter in wireless communications. PA usually operates in high non-linearity region which produces serious distortion at the output node. In practice, PA is operated at power back-off mode to meet the linearity requirement that substantially degrades power added efficiency (PAE). The linearization technique is required to meet the linearity and PAE specifications. This thesis primarily targets at the design and implementation of low voltage self-bias mixer and high-linearity PA for 5 GHz band CMOS RF front-end. The design goals of the mixer are low voltage operation, high conversion gain (CG), high linearity, and high port-to-port isolations. The PA design uses a post-distortion linearizing technique to achieve high linear output power, high PAE and low error vector magnitude (EVM).
In the thesis, Chapter 2 proposes an AC-coupling folded-switch double balanced mixer (DBM) that uses a novel low-voltage, low power self-bias current reuse technique in taiwan semiconductor manufacturing company (tsmcTM) standard 90 nm CMOS technology. At low supply voltage operation, the proposed DBM obtains good third-order intermodulation intercept point (IIP3) and CG at 5 GHz band. At the supply voltage of 0.7 V, the mixer achieves the best figure of merit (FOM) of 15.5 at 5 GHz band. Two designed mixers are combined with a differential low noise amplifier (DLNA), a poly-phase filter, and two buffer amplifiers to form a 5-6 GHz direct-conversion receiver (DCR) architecture. The DCR achieves a CG of 26 dB with a noise figure (NF) of 2.7 dB from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP3 of the DCR is -12 dBm.
The first stage of a DCR is typically low noise amplifier (LNA) and requests a minimum NF to improve the sensitivity of the receiving chain. Chapter 3 adopts a thin-film process of integrated passive device (IPD) technology which improves the NF of LNA. Our design combines standard 0.18 m CMOS process, IPD and flip-chip package technologies with a vertical heterogeneous integration to achieve a CMOS-IPD LNA. This fully integrated LNA improves an NF of 0.6 dB as compared to as compared to its counterpart without IPD. The CMOS-IPD LNA achieves the FOM of 16.72 at 5.2 GHz band.
Chapter 4 presents a CMOS-IPD PA which uses an impedance transformation ratio of 1:4. The 1:4 figure 8 power-combining transformer was also fabricated using IPD process to achieve high output power level. The PA uses an adaptive bias linearizer that extends the power gain and improves the linearity without extra power. This PA provides a saturation output power of 28 dBm and a PAE of 25 %. The CMOS-IPD PA improves the output power and PAE of 1.3 dB and 6 %, respectively, as compared to its counterpart without IPD.
Chapter 5 presents a 5 GHz CMOS PA using post-distortion linearizing technique. When the linearizer is turned on, the proposed PA improves the output power at 1 dB gain compression point (OP1dB). Only 0.2 dB discrepancy between the output P1dB and saturated output power is observed. The output P1dB of the PA with post-distortion linearizier is improved by 2.8 dB as compared to its counterpart without linearizer. Furthermore, the RF choke in the PA uses a wafer-level bondwire spiral inductor (BSL). The BSL achieves a Q of 32 which is three times higher than that of a conventional CMOS standard spiral inductor at 5 GHz. The output power and PAE of the PA with wafer-level BSL are improved by 1.6 dB and 7.3 % as compared to those of the fully integrated CMOS PA. Finally, Chapter 6 draws a brief conclusion.
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