| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 吳開文 | zh_TW |
| DC.creator | Kai-wen Wu | en_US |
| dc.date.accessioned | 2010-7-26T07:39:07Z | |
| dc.date.available | 2010-7-26T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=975201002 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文利用tsmc 0.18um 1P6M CMOS製程設計功率放大器，設計了兩個功率放大器，首先第一個電路設計在2.4 GHz，為一單級的功率放大器，藉由變壓器結合功率，以達成高輸出功率的目標。第二個電路同樣設計在2.4 GHz，也同樣是單級的功率放大器，設計反F類功率放大器，藉由諧波處理來增進效率，達成高效率的目標。
各電路特性量測如下：使用變壓器結合功率之功率放大器，增益為12.2 dB，S11為-12.0 dB，S22為-13.0 dB，輸出功率1-dB增益壓縮點為25.7 dBm，飽和輸出功率為27.1 dBm，輸出功率1-dB增益壓縮點效率為14.3 %，最大效率為14.7 %，同時，藉由本次的電流耐流量考量以及power cells的設計方式，可以提升電路特性，並且有很高的耐流量，量測到直流電流達到1.2 A，且電路安全無虞，並且此最大電流是在國家晶片中心(CIC)進行量測，已經將輸入訊號調至最大的狀態之下，因此估計應可有更大的耐流量；反F類功率放大器，增益為8.7 dB，S11為-16.4 dB，S22為-16.8 dB，輸出功率1-dB增益壓縮點為19.7 dBm，飽和輸出功率為21.1 dBm，輸出功率1-dB增益壓縮點效率為31.3 %，最大效率為31.3 %。
| zh_TW |
| dc.description.abstract | This thesis presents CMOS power amplifier (PA) implemented in 0.18um CMOS technology. The implemented circuits include two PA circuits. The first power amplifier is targeted for high output power. The power amplifier using power-combining transformer is presented. The second power amplifier is targeted for high-efficiency which power amplifier is based on the inverse class F technique.
The measured results are summarized as below: the PA with power-combining transformer technique achieves a power gain of 12.2 dB with input and output return losses of 12.0 dB and 13.0 dB, a 1-dB gain compression point (P1dB) of 25.7 dBm, a maximum output power of 27.1 dBm, a power added efficiency (PAE) at P1dB of 14.3 %, a maximum PAE of 14.7 %. The PA with inverse class F achieves a power gain of 8.7 dB with input and output return losses of 16.4 dB, and 16.8 dB, a P1dB of 19.7 dBm, a maximum output power of 21.1 dBm, a PAE at P1dB of 31.3 %, a maximum PAE of 31.3 %.
| en_US |
| DC.subject | 功率放大器 | zh_TW |
| DC.subject | power amplifier | en_US |
| DC.title | 使用變壓器結合功率之功率放大器與反F類功率放大器研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Implementations on Power Amplifier Using Power-Combining Transformer and Inverse Class F Power Amplifier Techniques | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |