dc.description.abstract | Three-dimensional (3-D) integration technology using through-silicon via (TSV) is one emerging integrated circuit (IC) technology. The 3-D integration technology offers many advantages over the 2-D integration technology, such as power reduction, performance improvement,
heterogeneous integration, etc. However, many challenges should be overcome before the volume production of 3-D ICs become possible. Among these challenges, test and yield are two key challenges. Effective test and yield-enhancement techniques thus are important for 3-D ICs.
A 3-D IC consists of multiple dies connected vertically by TSVs. Since the dies may come from different sources, a standardized test control interface for integrating the designfor-testability (DFT) circuits in each die thus is imperative. In the first part of this thesis, we propose test interfaces for the logic and memory dies, and these test interfaces can be integrated in a hierarchical method. The test interfaces can support the prebond, midbond, postbond, and final tests. The minimum number of required test pads of the proposed test interfaces is only four. Furthermore, the test interfaces are compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the
proposed test interfaces is very small, which is about 0.24% for the ITC’99 b19 benchmark using TSMC 0.18μm CMOS technology. A 3-D test chip is also implemented to emonstrate the proposed test integration methodology.
In the second part of this thesis, we propose a programmable built-in self-test (BIST)
scheme for JEDEC wide I/O DRAMs. One main difference between a wide I/O DRAM and a general DRAM is the minimum burst length. The minimum burst length of a wide I/O DRAM and a general DRAM is 2 and 1, respectively. That causes that using existing March test algorithms to test wide I/O DRAM cannot achieve 100% fault coverage for coupling faults. A test algorithm thus is proposed to achieve 100% fault coverage of coupling faults as well. Furthermore, a test pin reusing methodology is proposed to reuse the test pins of boundary scan of the wide I/O DRAM to control the BIST circuit. Thus, the number of pins of the DRAM die with BIST is the same as that of the DRAM die without BIST. inally, the programmability of the proposed BIST can support various March test algorithms and various memory configurations. Experimental results show that the area cost of the BIST is very small, which is about 0.32% for 32G-bit DRAM using TSMC 90nm CMOS technology.
In the third part of this thesis, we present yield-enhancement techniques for 3-D RAMs. An inter-die redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with inter-die redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is also proposed to perform the 3-D RAM repair. Its built-in redundancy analysis (BIRA) module
can allocate the inter-die redundancies efficiently. Simulation results show that the proposed yield-enhancement techniques can drastically improve the final yield of 3-D RAMs. We simulated 10 wafers and each wafer has 4350 RAM dies. The size of a RAM die is 512K bytes, and each RAM die has two blocks. The size of a block is 256K bytes and each block has two spare rows and two inter-die spare columns. Also, the fault distribution of the simulated RAM dies
with 60% single-cell faults, 20% faulty rows, and 20% faulty columns is assumed. The yield improvement of 3-D RAMs with proposed yield-enhancement techniques is 9.588%, 9.584%, and 14.462% by using die-to-die, die-to-wafer, and wafer-to-wafer bonding techniques. And the area overhead of the proposed BISR scheme in a RAM die is small, which is about 1.77% for a 2M-bit RAM die. | en_US |