| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 涂祐豪 | zh_TW |
| DC.creator | Yo-hao Tu | en_US |
| dc.date.accessioned | 2010-10-19T07:39:07Z | |
| dc.date.available | 2010-10-19T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=975201023 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文提出一個具寬頻操作、擁有多個相位輸出並具有相位誤差較正電路的延遲鎖定迴路。為了得到更大的運用效能，還具有一個頻率倍頻器可以另外產生一個倍頻的時脈訊號。在延遲鎖定迴路中，利用多頻段技巧，使電路可以操作在較寬的操作頻帶之下。而為了減少因為靜態相位誤差帶來的效應，利用一個時間放大器所組成的校正迴路，可以達到修正相位誤差的效果。延遲鎖定迴路整體電路架構若要操作在高速之下，在設計上有一定的難度，故將架構中的多相位輸出，透過邊緣合成的技巧，即可得到一個高速的時脈訊號，而延遲鎖定迴路本身卻可以保持較低速的操作頻率。另外，延遲鎖定迴路之多相位輸出可提供給發射端電路(Transmitter, Tx)使用，作為其時脈產生器。
本論文之具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器使用TSMC 180 nm 1P6M CMOS製程實現晶片，其操作頻率範圍可從80 MHz到600 MHz，並且擁有12個相位的輸出，而頻率倍頻器範圍可從0.96 GHz 到 2.5 GHz。整體晶片面積為745 × 745 um2，核心電路的面積為356 × 356 um2。電路在操作電壓為1.8 V時，最大功率消耗為19.2 mW。延遲鎖定迴路輸出訊號(600 MHz)之最大抖動量(P2P Jitter)的為21.22 ps，方均根抖動量(RMS Jitter)為2.62 ps。而頻率倍頻器的輸出訊號(2.4 GHz)之最大抖動量(P2P Jitter)為35.11 ps，方均根抖動量(RMS Jitter)為4.28 ps。本論文提出的改良式責任週期校正電路和相位誤差補償迴路皆能有效的操作，並且相位誤差可以得到約 33.33 % 的改善。
| zh_TW |
| dc.description.abstract | This study presents a wide-range and multiphase DLL-based clock generator with the Phase Error Compensation loop. For more applications, we proposed a frequency multiplier to synthesize a combined clock. In this voltage control delay line, we take the multi-gain technique to achieve the wide-range operation frequency. And we proposed a Phase Error Compensation loop with the timing amplifier. It is difficult to realize a DLL in high operation frequency, so using multiphase technique can solve this problem. And the multiphase architecture can become the clock generator of a Transmitter (Tx).
This study was implemented by TSMC 180 nm 1P6M CMOS process. The input frequency range of the proposed DLL is from 80 MHz to 600 MHz with 12-phase output. The output range of frequency multiplier is from 0.96 GHz to 2.5 GHz. The chip area is 0.745 × 0.745 mm2 and the core area is 0.356 × 0.356 mm2. The power consumption is 19.2 mW at a supply of 1.8 V. The peak-to-peak jitter and rms jitter of delay locked loop are 21.22 ps and 2.62 ps at 800 MHz. The peak-to-peak jitter and rms jitter of frequency multiplier are 35.11 ps and 4.28 ps at 2.4 GHz. And the Phase Error Compensation loop can improve 33.33% of the static phase error.
| en_US |
| DC.subject | 阻塞鎖定 | zh_TW |
| DC.subject | 責任週期校正電路 | zh_TW |
| DC.subject | 半穿透式架構 | zh_TW |
| DC.subject | 頻率倍頻器 | zh_TW |
| DC.subject | 延遲鎖定迴路 | zh_TW |
| DC.subject | Stuck Locking | en_US |
| DC.subject | Frequency Multiplier (FM) | en_US |
| DC.subject | Half Transparent (HT) | en_US |
| DC.subject | Duty Cycle Corrector (DCC) | en_US |
| DC.subject | Delay-Locked Loop (DLL) | en_US |
| DC.title | 具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | A Wide Range Delay-Locked Loop with Phase Error Calibration and Frequency Multiplier | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |