| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 劉許驊 | zh_TW |
| DC.creator | Hsu-Hua Liu | en_US |
| dc.date.accessioned | 2010-11-17T07:39:07Z | |
| dc.date.available | 2010-11-17T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=975201029 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著資料傳輸速率需求的增加，對於輸入與輸出的頻寬限制也與日俱增，因此高速串列傳輸系統逐漸取代傳統的並列傳輸方式，例如應用在乙太網路及光纖網路上的OC-192，與著重於有線或是匯流排上的應用有PCI-E、SATA…等系統，在這些規格所傳輸的速率已達到 Gbps的等級。本論文之設計主要針對串列有線傳輸系統中的SATA接收端規格為設計藍圖，採用雙迴路的方式實現，基本架構為延遲鎖定迴路，並加上頻率偏移校正迴路解決頻率偏移的問題，利用全速率取樣方式實現資料回復電路。
本論文實現應用於3 Gbps的串列傳輸系統中之資料回復電路。此系統中具有延遲鎖定迴路與頻率偏移校正迴路之雙迴路設計。延遲鎖定迴路用來做資料與時脈間的相位追鎖，但由於延遲鎖定迴路本身並無頻率追鎖的能力，所以當資料與時脈間存在頻率偏移時可能因此造成系統的不穩定，故加上頻率偏移校正迴路在資料與時脈間產生頻率偏移時，提供額外的相位補償給延遲鎖定迴路，最後延遲鎖定迴路校準時脈到達最佳取樣位置。
本論文之全速率資料回復電路使用TSMC 90 nm 1P9M CMOS製程實現晶片，其輸入資料為3 Gbps差動訊號，操作時脈為四相位3 GHz訊號。整體晶片面積為534 um ? 556 um，核心電路的面積為325 um ? 278 um。電路在操作電壓為1.2V時，功率消耗為23.8mW。
| zh_TW |
| dc.description.abstract | As the increase of the demands for the high speed data rate, the input-output bandwidth will progress with each passing day. Therefore, the high speed serial transmission systems have replaced traditional parallel transmission systems gradually. For example, OC-192 is applied in Gigabit Ethernet and Fiber channel. PCI-E and SATA are use in wire or bus serial links. Most of the system operates at the data rate attending to the level of Gbps. For the design of the SATA receiver circuit system, the study introduces the dual-loop-based data recovery circuit architecture, and develops the circuit on the full-rate sampling data technique. The architecture consists of a delay-locked loop (DLL) and a frequency offset calibration loop. Thus, based on the calibration loop, the issue of the frequency offset can be eliminated.
The data recovery circuit architecture is implemented for the application to the 3 Gbps serial link system. The data recovery architecture is composed of DLL and the frequency offset calibration loop. Traditionally, due to the only phase tracking capability for DLL, use DLL to track the phase difference between clock and data may cause the frequency offset problem. It means that, when the frequency difference exists between the clock and data, the DLL can not lock in phase and yields the unstable system. Accordingly, the use of the frequency offset calibration loop can compensate the phase in tracking data. Finally, as the DLL adjusts the delay clock phase, the data is recovered in success.
This study implements the full-rate data recovery circuit in TSMC 90 nm 1P9M CMOS process. The input signal is the 3 Gbps differential data, and the input clock is 3 GHz with the 4 phase signal. The chip area is 534 um ? 556 um and the core area is 325 um ? 278 um. The power consumption is 30 mW at supply of 1.2V.
| en_US |
| DC.subject | 延遲鎖定迴路 | zh_TW |
| DC.subject | 資料回復電路 | zh_TW |
| DC.subject | 時脈與資料回復電路 | zh_TW |
| DC.subject | Delay-locked loop | en_US |
| DC.subject | Clock and data recovery | en_US |
| DC.subject | Data recovery | en_US |
| DC.title | 應用於具有擴展頻譜串列資料之每秒30億位元全速率資料回復電路 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and Implementation of 3 Gbps Full-Rate Data Recovery Circuit for Serial Link Data Transmission with Spread-Spectrum Clocking | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |