| dc.description.abstract | This dissertation proposes the photodetectors using cheaper silicon material combined
with standard CMOS technology without any process modifications. To enable the
cost-effective implementation of the optical short-distance interconnection, Si CMOS
technologies is a good, low-cost approach for general 850 nm transmitter and provide a
universal platform for the monolithic integration of available, complex, and high-speed
circuits with Si photodetectors to form an all-Si optical receiver (OEIC).
One of the most crucial issues for 850 nm Si photodiodes in standard CMOS technology
is the response speed. Because the penetration depth (∼ 20 μm) of the 850 nm-wavelength
light into Si is much deeper than that of the depth of the depletion (∼ 2 μm) in the surface
p-n diodes. As a result, a large portion of carriers is generated in the Si substrate and
diffuse in all directions. The slow diffusion carriers will reach the depletion region and led
to the slow response of the p-n PD.
Researchers have studied several device layouts to optimize device performance. Silicon
photodiodes (PDs) with different layouts in standard 0.18-μm CMOS technology are
systematically presented and discussed first in this dissertation. Different layout geometries
of PDs are realized including conventional rectangle, square and octagon layouts. A basic
p-n PD with octagon layout demonstrates higher responsivity and lower capacitance with
improved bandwidth. Therefore, the vertically illuminated PDs with octagonal layout are
used in this dissertation.
To improve the speed characteristics of the photodetector, three methods are proposed to
improve the bandwidth. First, a basic p-n PD with body contact presents a method to
eliminate the slow photocarriers by adopting a body contact design to create a current flow
under the PD to remove the slow diffusion carriers.. With the appropriate bias between PD
and body contact, a low bias and high-speed PD can be achieved for practical applications.
The 3dB bandwidth of PD is 2.46 GHz at low bias 3 V.
Secondly, the edge-illuminated Si PDs with standard CMOS technology by employing
an MEMS process to expose the coupling edge surface is realized. A single-mode lensed
fiber is employed to inject light into the depletion region of the PD, thereby limiting and
reducing the diffusive carriers within the bulk Si substrate. Consequently, the
edge-illuminated PD with conventional rectangle layout shows the improved 3-dB
bandwidth from 1.4 GHz to 2.6 GHz in comparison to the vertically illuminated Si PDs.
The third method is that using deep n-well implantation in standard CMOS technology
to block the slow diffusion carriers from substrate. Two different bias schemes (normal
bias and extra bias) on the deep n-well are used to analyze the effects of deep n-well bias on the bandwidth and gain-bandwidth performances of Si PDs. The extra bias in the PD
not only blocks the hole and collects electrons from the substrate, but also improves the PD
performance. This design achieves the highest bandwidth (8.7 GHz) and a large
gain-bandwidth product of 542 GHz with a reverse bias of 11.45 V and an extra voltage of
11.45 V but low-magnitude of output signal in standard CMOS technology. This is the
highest bandwidth reported for silicon photodetectors fabricated using standard CMOS
technology and the highest gain-bandwidth product in 0.18 µm CMOS technology. In
addition to bandwidth, excess noise measurement is a way to confirm the effect of
excluding substrate carrier. Si PDs in this dissertation with extra bias in the deep n-well
demonstrates the lowest noise figure (noise factor) of 5.3 due to the removal of slow
diffusion carriers. | en_US |