dc.description.abstract | In recent year, owing to the development of network and processor, the requirement of the high-speed data transmission has become the main motivation of transmission system. The conventional parallel bus shows the serious restriction while operating in the gigahertz range. As a result, the high-speed serial link technology is widely used so far for today’s data transmission system.
This thesis presents a half-rate and dual-looped clock and data recovery (CDR) for the 3-Gbps data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only one clock instead of the multi-phase clock, and the complexity of the clock distribution network could be mitigated than counterpart. In addition, the control- mirroring signal stemming from the PLL locking signal indicates the robust of data delay segment of DDW in the process, voltage, and temperature variations. In terms of the bandwidth setting, both the DR and PLL bandwidth optimization for jitter suppression and the shortened acquisition time could also come to compromise. Besides, once the input data has frequency deviation, the use of the frequency detector would detect such data frequency difference and coarsely adjust the tracking phase in success.
This thesis implements the dual-looped CDR circuit in TSMC 180 nm 1P6M CMOS process. Operating at the 3-Gbps data rate and 1.5-GHz clock frequency, the estimated peak to peak jitter of the recovered clock is 14.7 ps, and the recovered data jitter is less than 15.8 ps. The core area of CDR occupies 1.13 mm2.
| en_US |