| dc.description.abstract | Stereo vision has been widely used in many fields and our daily life, such as virtual reality, auto-navigation of mobile robot, auto-tracking and security monitoring system, and 3D human-machine interaction system, etc. Due to high computational complexity of stereo vision algorithm and needs of real-time system performance, it needs to design a real-time stereo vision hardware platform.
In this thesis, we propose a real-time stereo vision system architecture and it is suitable for hardware implementation. Based on high-level system hardware design methodology, our proposed method finds regions of interest (ROI), such as big obstacles, from un-calibrated stereo images by image preprocessing and connected component labeling, and then processes local stereo matching with block-based match metric, SAD, to get disparity, and finally gets depth information from a lookup disparity-depth relation table. About hardware implementation, we use IDEF0 to set up systematic stratum module at first, and then perform the discrete modeling of the software-proved algorithm with GRAFCET, and translate VHDL hardware circuit from GRAFCET models. We design and implement not only image preprocessing IPs and stereo matching IP, but also pipeline controller to integrate all IPs into a high-speed and parallel architecture stereo vision system, and finally we verify hardware system on FPGA devices.
The result shows our system performance can achieve 28 frames per second (FPS) stereo images depth estimation under 92.34MHz clock rate. It fully satisfies the needs of real-time performance and accuracy for stereo vision application in low-complexity scene. By comparison with traditional stereo vision solution using high-performance CPU or GPU, our stereo vision system has advantages of simple, low-cost, and high-performance.
| en_US |