| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳彥龍 | zh_TW |
| DC.creator | Yen-Lung Chen | en_US |
| dc.date.accessioned | 2010-7-25T07:39:07Z | |
| dc.date.available | 2010-7-25T07:39:07Z | |
| dc.date.issued | 2010 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=985201018 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著製程的演進，元件的尺寸逐漸縮小，積體電路已經來到奈米(nanometer)製程技術的時代。由於元件尺寸的微縮，製程變異對於電路效能的影響日益嚴重，特別是針對較敏感的類比電路，導致晶片製造良率(yield)下降，因此，積體電路的製造可行性設計(Design for Manufacturability, DFM)或良率導向設計(Design for Yield, DFY)，已成為相當熱門的研究議題。主要的概念，是希望在電路設計初期，把製造過程中可能產生的製程變異現象考慮進來，事先評估對電路效能的影響；若分析之良率不佳，及早在設計初期改良電路。這樣不但能達到提升良率的效果，還能減少重新設計或重新下線(re-spin)的時間，大幅降低IC設計成本。
本論文提一個改善良率(yield enhancement)的流程，以充電幫浦的鎖相迴路(charge pump phase-locked loop, CPPLL)為研究實例。在盡量維持原始電路效能前提下，藉由模擬退火法(simulated annealing)調整電路元件尺寸，來降低電路效能對於製程變異的敏感度(process variation sensitivity)，進而達到提升良率的目標。
| zh_TW |
| dc.description.abstract | Along with the evolution of manufacturing process, the size of integrated circuits has shrunk into the nanometer scale. The process variation influence on circuit performance is more and more serious, especially for analog circuits. Therefore, design-for-manufacturability (DFM) and design-for-yield (DFY) techniques have become popular research directions in recent years. The main concept of DFM and DFY is to consider the process variation effects in early stage of IC designs. If we can evaluate the impacts of circuit performance under process variations in advance, the circuit yield could be improved at early stages to reduce the re-design cycles and re-spin cost.
In this thesis, we propose a yield enhancement flow for the phase-locked loop circuits. According to the relationship between transistor sizes and process variation sensitivity, the proposed approach adjusts the transistor sizes to reduce process variation sensitivity of CPPLL circuit with similar nominal performance. In order to enhance yield of circuits.
| en_US |
| DC.subject | 鎖相迴路 | zh_TW |
| DC.subject | 良率 | zh_TW |
| DC.subject | Yield | en_US |
| DC.subject | PLL | en_US |
| DC.title | 以降低製程變異敏感度的方法提升鎖相迴路良率之改進策略 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | An Enhanced Yield Optimization Approach for CPPLL via Process Sensitivity Reduction | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |