| dc.description.abstract | As the process technology advances, the device size of integrated circuits continues to shrink into the nanometer scale. However, the device size is nearing its physical limits. Besides, interconnect delays are also growing, incurring the bottleneck of chip performance. Therefore, designers are thinking of moving to another point to develop a new generation of design technologies. Three dimensional integrated circuits (3D IC) are proposed as one technology to solve these problems. However, although 3D IC designs have better chip size, performance, and power consumption than 2D IC designs have, many emergent issues are occurred. Temperature is one of important issues and cannot be ignored. The temperature issue is mainly from the stacking technology which makes the thermal inside a chip cannot be dissipated easily. Thus, an overheating chip will incur the chip failed. Thermal through-silicon-via (TTSV) insertion technology is an effective method to dissipate the thermal in 3D IC. Since the size of a TTSV is much larger than that of a standard cell, space shortage and layout modification can be avoided if the TTSV location are planned in an early physical design stage. Thus, many researches proposed TTSV insertion by a push-block method to solve this issue during floorplanning.
In this thesis, we propose a new viewpoint for TTSV insertion. The required number of TTSVs for each block is estimated and is used to enlarge the block before floorplanning. During floorplanning, we not only minimize area and wirelength, but also maximize the effect of fusion of TTSV area. Our objective is to satisfy the target temperature inside a chip with minimum number of TTSVs.
| en_US |